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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:037625/0564   Pages: 20
Recorded: 01/29/2016
Conveyance: MERGER (SEE DOCUMENT FOR DETAILS).
Total properties: 39
1
Patent #:
5831312
Issue Dt:
11/03/1998
Application #:
08630024
Filing Dt:
04/09/1996
Title:
ELECTROSTIC DISCHARGE PROTECTION DEVICE COMPRISING A PLURALITY OF TRENCHES
2
Patent #:
5886375
Issue Dt:
03/23/1999
Application #:
08735007
Filing Dt:
10/22/1996
Title:
SRAM HAVING IMPROVED SOFT-ERROR IMMUNITY
3
Patent #:
5966604
Issue Dt:
10/12/1999
Application #:
08890363
Filing Dt:
07/09/1997
Title:
METHOD OF MANUFACTURING MOS COMPONENTS HAVING LIGHTLY DOPED DRAIN STRUCTURES
4
Patent #:
5877615
Issue Dt:
03/02/1999
Application #:
08965581
Filing Dt:
11/06/1997
Title:
DYNAMIC INPUT REFERENCE VOLTAGE ADJUSTER
5
Patent #:
5960285
Issue Dt:
09/28/1999
Application #:
08975490
Filing Dt:
11/21/1997
Title:
FLASH EEPROM DEVICE
6
Patent #:
5907172
Issue Dt:
05/25/1999
Application #:
08998312
Filing Dt:
12/24/1997
Title:
SPLIT-GATE FLASH MEMORY CELL STRUCTURE
7
Patent #:
5872036
Issue Dt:
02/16/1999
Application #:
08998331
Filing Dt:
12/24/1997
Title:
METHOD OF MANUFACTURING A SPLIT-GATE FLASH MEMORY CELL
8
Patent #:
5904520
Issue Dt:
05/18/1999
Application #:
09002930
Filing Dt:
01/05/1998
Title:
METHOD OF FABRICATING A CMOS TRANSISTOR
9
Patent #:
6057208
Issue Dt:
05/02/2000
Application #:
09057905
Filing Dt:
04/09/1998
Title:
METHOD OF FORMING SHALLOW TRENCH ISOATION
10
Patent #:
6025241
Issue Dt:
02/15/2000
Application #:
09073576
Filing Dt:
05/06/1998
Title:
METHOD OF FABRICATING SEMICONDUCTOR DEVICES WITH SELF-ALIGNED SILICIDE
11
Patent #:
6001733
Issue Dt:
12/14/1999
Application #:
09164856
Filing Dt:
10/01/1998
Title:
METHOD OF FORMING A DUAL DAMASCENE WITH DUMMY METAL LINES
12
Patent #:
6071776
Issue Dt:
06/06/2000
Application #:
09186748
Filing Dt:
11/05/1998
Title:
FLASH MEMORY STRUCTURE AND METHOD OF MANUFACTURE
13
Patent #:
6153498
Issue Dt:
11/28/2000
Application #:
09191247
Filing Dt:
11/12/1998
Title:
METHOD OF FABRICATING A BURIED CONTACT
14
Patent #:
6291112
Issue Dt:
09/18/2001
Application #:
09191762
Filing Dt:
11/13/1998
Title:
METHOD OF AUTOMATICALLY FORMING A RIM PHASE SHIFTING MASK
15
Patent #:
6146960
Issue Dt:
11/14/2000
Application #:
09195744
Filing Dt:
11/18/1998
Title:
METHOD OF FORMING MIXED MODE DEVICES
16
Patent #:
6265780
Issue Dt:
07/24/2001
Application #:
09203035
Filing Dt:
12/01/1998
Title:
DUAL DAMASCENE STRUCTURE FOR THE WIRING-LINE STRUCTURES OF MULTI-LEVEL INTERCONNECTS IN INTEGRATED CIRCUIT
17
Patent #:
6140196
Issue Dt:
10/31/2000
Application #:
09203711
Filing Dt:
12/02/1998
Title:
METHOD OF FABRICATING HIGH POWER BIPOLAR JUNCTION TRANSISTOR
18
Patent #:
6153528
Issue Dt:
11/28/2000
Application #:
09205912
Filing Dt:
12/04/1998
Title:
METHOD OF FABRICATING A DUAL DAMASCENE STRUCTURE
19
Patent #:
6150205
Issue Dt:
11/21/2000
Application #:
09227761
Filing Dt:
01/08/1999
Title:
METHOD OF FABRICATING DUAL GATE
20
Patent #:
6169028
Issue Dt:
01/02/2001
Application #:
09237787
Filing Dt:
01/26/1999
Title:
METHOD FABRICATING METAL INTERCONNECTED STRUCTURE
21
Patent #:
6190981
Issue Dt:
02/20/2001
Application #:
09243740
Filing Dt:
02/03/1999
Title:
METHOD FOR FABRICATING METAL OXIDE SEMICONDUCTOR
22
Patent #:
6268283
Issue Dt:
07/31/2001
Application #:
09248159
Filing Dt:
02/09/1999
Title:
METHOD FOR FORMING DUAL DAMASCENE STRUCTURE
23
Patent #:
5972764
Issue Dt:
10/26/1999
Application #:
09270026
Filing Dt:
03/16/1999
Title:
METHOD FOR MANUFACTURING MOS TRANSISTOR
24
Patent #:
6060357
Issue Dt:
05/09/2000
Application #:
09286139
Filing Dt:
04/05/1999
Title:
METHOD OF MANUFACTURING FLASH MEMORY
25
Patent #:
5981325
Issue Dt:
11/09/1999
Application #:
09299255
Filing Dt:
04/26/1999
Title:
METHOD FOR MANUFACTURING CMOS
26
Patent #:
6194279
Issue Dt:
02/27/2001
Application #:
09340929
Filing Dt:
06/28/1999
Title:
FABRICATION METHOD FOR GATE SPACER
27
Patent #:
6265274
Issue Dt:
07/24/2001
Application #:
09431954
Filing Dt:
11/01/1999
Title:
METHOD OF A METAL OXIDE SEMICONDUCTOR ON A SEMCONDUCTOR WAFER
28
Patent #:
6281554
Issue Dt:
08/28/2001
Application #:
09531905
Filing Dt:
03/20/2000
Title:
Electrostatic discharge protection circuit
29
Patent #:
6353247
Issue Dt:
03/05/2002
Application #:
09557513
Filing Dt:
04/25/2000
Title:
High voltage electrostatic discharge protection circuit
30
Patent #:
6294415
Issue Dt:
09/25/2001
Application #:
09558220
Filing Dt:
04/26/2000
Title:
Method of fabricating a mos transistor
31
Patent #:
6436764
Issue Dt:
08/20/2002
Application #:
09590721
Filing Dt:
06/08/2000
Title:
METHOD FOR MANUFACTURING A FLASH MEMORY WITH SPLIT GATE CELLS
32
Patent #:
6446647
Issue Dt:
09/10/2002
Application #:
09597744
Filing Dt:
06/19/2000
Title:
CASSETTE HOLDER FOR CLEANING EQUIPMENT
33
Patent #:
6436759
Issue Dt:
08/20/2002
Application #:
09764330
Filing Dt:
01/19/2001
Publication #:
US20020098649
Pub Dt:
07/25/2002
Title:
METHOD FOR FABRICATING A MOS TRANSISTOR OF AN EMBEDDED MEMORY
34
Patent #:
6436765
Issue Dt:
08/20/2002
Application #:
09779540
Filing Dt:
02/09/2001
Publication #:
US20020110984
Pub Dt:
08/15/2002
Title:
METHOD OF FABRICATING A TRENCHED FLASH MEMORY CELL
35
Patent #:
6410373
Issue Dt:
06/25/2002
Application #:
09845438
Filing Dt:
04/30/2001
Title:
METHOD OF FORMING POLYSILICON THIN FILM TRANSISTOR STRUCTURE
36
Patent #:
6461959
Issue Dt:
10/08/2002
Application #:
09885049
Filing Dt:
06/21/2001
Title:
METHOD FOR FABRICATION OF A CONTACT PLUG IN AN EMBEDDED MEMORY
37
Patent #:
6486496
Issue Dt:
11/26/2002
Application #:
09994322
Filing Dt:
11/26/2001
Publication #:
US20020153527
Pub Dt:
10/24/2002
Title:
POLYSILICON THIN FILM TRANSISTOR STRUCTURE
38
Patent #:
6483142
Issue Dt:
11/19/2002
Application #:
10108611
Filing Dt:
03/27/2002
Publication #:
US20020167090
Pub Dt:
11/14/2002
Title:
DUAL DAMASCENE STRUCTURE HAVING CAPACITORS
39
Patent #:
7378740
Issue Dt:
05/27/2008
Application #:
11196038
Filing Dt:
08/02/2005
Publication #:
US20050263876
Pub Dt:
12/01/2005
Title:
DUAL DAMASCENE STRUCTURE FOR THE WIRING-LINE STRUCTURES OF MULTI-LEVEL INTERCONNECTS IN INTEGRATED CIRCUIT
Assignor
1
INTELLECTUAL VENTURES FUND 74 LLC
Exec Dt:
08/27/2015
Assignee
1
INTELLECTUAL VENTURES HOLDING 81 LLC
7251 W LAKE MEAD BLVD
SUITE 300
LAS VEGAS, NEVADA 89128
Correspondence name and address
FOLEY & LARDNER LLP
150 EAST GILMAN STREET
VEREX PLAZA
MADISON, WI 53703

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