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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09206454
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Filing Dt:
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12/07/1998
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Title:
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APPARATUS FOR RECEIVING DATA FROM A SYNCHRONOUS RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09206793
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Filing Dt:
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12/07/1998
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Title:
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METHOD FOR RECEIVING DATA FROM A SYNCHRONOUS RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09212047
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Filing Dt:
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12/15/1998
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Title:
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METHOD FOR CONTROLLING PIPELINED MEMORY ACCESS REQUESTS
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09212139
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Filing Dt:
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12/15/1998
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Title:
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APPARATUS FOR CONTROLLING PIPELINED MEMORY ACCESS REQUESTS
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09221210
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Filing Dt:
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12/23/1998
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Publication #:
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Pub Dt:
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01/10/2002
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Title:
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METHOD FOR CONTROLLING OUT OF ORDER ACCESSING TO A MULTIBANK MEMORY
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09239633
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Filing Dt:
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01/29/1999
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Title:
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PROGRAMMABLE GRAPHICS MEMORY METHOD
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Patent #:
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Issue Dt:
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01/27/2004
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Application #:
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09239911
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Filing Dt:
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01/29/1999
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Publication #:
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Pub Dt:
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06/20/2002
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Title:
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METHOD TO ACCESS MEMORY BASED ON A PROGRAMMABLE PAGE LIMIT
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09240514
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Filing Dt:
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01/29/1999
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Title:
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PROGRAMMABLE GRAPHICS MEMORY APPARATUS
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09240526
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Filing Dt:
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01/29/1999
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Title:
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DEVICE TO ACCESS MEMORY BASED ON A PROGRAMMABLE PAGE LIMIT
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09244371
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Filing Dt:
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02/04/1999
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Title:
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METHOD FOR MULTIPLEXING BUS INTERFACES ON A COMPUTER EXPANSION BUS
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09244598
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Filing Dt:
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02/04/1999
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Title:
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APPARATUS FOR MULTIPLEXING BUS INTERFACES ON A COMPUTER EXPANSION BUS
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09248559
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Filing Dt:
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02/11/1999
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Title:
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APPARATUS FOR CONFIGURING DEVICES ON A COMMUNICATIONS CHANNEL
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09248598
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Filing Dt:
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02/11/1999
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Title:
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METHOD OF CONFIGURING DEVICES ON A COMMUNICATIONS CHANNEL
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09258230
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Filing Dt:
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02/26/1999
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Title:
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APPARATUS FOR ENABLING SYSTEM OPERATION
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09258236
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Filing Dt:
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02/26/1999
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Title:
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METHOD OF ENABLING SYSTEM OPERATION
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09283335
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Filing Dt:
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03/31/1999
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Title:
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BIDIRECTIONAL DATA TRANSFER DURING BUFFER FLUSHING OPERATIONS
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Patent #:
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Issue Dt:
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01/19/2010
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Application #:
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09285292
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Filing Dt:
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04/02/1999
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Title:
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DETECTING CYP24 EXPRESSION LEVEL AS A MARKER FOR PREDISPOSITION TO CANCER
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09289151
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Filing Dt:
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04/08/1999
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Title:
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TECHNIQUE TO AUTOMATICALLY NOTIFY AN OPERATING SYSTEM LEVEL APPLICATION OF A SYSTEM MANAGEMENT EVENT
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09289152
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Filing Dt:
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04/08/1999
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Title:
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APPARATUS FOR AUTOMATICALLY NOTIFYING OPERATING SYSTEM LEVEL APPLICATIONS OF THE OCCURRENCE OF SYSTEM MANAGEMENT EVENTS
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09324397
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Filing Dt:
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06/03/1999
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Title:
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AGP CLOCK START/STOP DETECTION CIRCUIT
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09327278
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Filing Dt:
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06/03/1999
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Title:
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FUNCTIONAL LEVEL CONFIGURATION OF INPUT-OUTPUT TEST CIRCUITRY
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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09327284
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Filing Dt:
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06/07/1999
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Title:
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APPARATUS FOR MULTIPLEXING SIGNALS
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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09327291
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Filing Dt:
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06/07/1999
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Title:
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METHOD FOR MULTIPLEXING SIGNALS THROUGH I/O PINS
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09327412
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Filing Dt:
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06/07/1999
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Title:
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METHOD FOR CONFIGURING BUS ARCHITECTURE THROUGH SOFTWARE CONTROL
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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09327413
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Filing Dt:
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06/07/1999
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Title:
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APPARATUS FOR CONFIGURING BUS ARCHITECTURE THROUGH SOFTWARE CONTROL
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09332278
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Filing Dt:
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06/12/1999
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Title:
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METHOD FOR SELECTIVELY ENCODING BUS GRANT LINES TO REDUCE I/O PIN REQUIREMENTS
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09332279
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Filing Dt:
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06/12/1999
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Title:
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APPARATUS FOR SELECTIVELY ENCODING BUS GRANT LINES TO REDUCE I/O PIN REQUIREMENTS
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09349422
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Filing Dt:
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07/07/1999
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Title:
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MECHANISM TO EXPAND ADDRESS SPACE OF A SERIAL BUS
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09349816
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Filing Dt:
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07/09/1999
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Title:
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TIMING CIRCUIT FOR HIGH SPEED MEMORY
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09352718
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Filing Dt:
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07/13/1999
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Title:
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METHOD FOR SYNCHRONIZING STROBE AND DATA SIGNALS FROM A RAM
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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09352719
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Filing Dt:
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07/13/1999
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Title:
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APPARATUS FOR SYNCHRONIZING STROBE AND DATA SIGNALS RECEIVED FROM A RAM
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Patent #:
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Issue Dt:
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05/07/2002
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Application #:
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09352720
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Filing Dt:
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07/13/1999
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Title:
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APPARATUS FOR SUPPORTING MULTIPLE DELAYED READ TRANSACTIONS BETWEEN COMPUTER BUSES
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09352721
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Filing Dt:
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07/13/1999
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Title:
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METHOD FOR SUPPORTING MULTIPLE DELAYED READ TRANSACTIONS BETWEEN COMPUTER BUSES
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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09352722
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Filing Dt:
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07/13/1999
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Title:
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METHOD FOR PROVIDING FAST MEMORY DECODE USING A BANK CONFLICT TABLE
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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09352723
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Filing Dt:
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07/13/1999
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Title:
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APPARATUS FOR PROVIDING FAST MEMORY DECODE USING A BANK CONFLICT TABLE
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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09363547
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Filing Dt:
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07/29/1999
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Title:
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BUS ARBITRATION
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09363594
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Filing Dt:
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07/29/1999
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Title:
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SYSTEM AND METHOD FOR REGULATING DATA CAPTURE IN RESPONSE TO DATA STROBE USING PREAMBLE, POSTAMBLE AND STROBE SIGNATURE
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09363604
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Filing Dt:
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07/29/1999
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Title:
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REDUCING MEMORY LATENCY BY NOT PERFORMING BANK CONFLICT CHECKS ON IDLE BANKS
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Patent #:
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Issue Dt:
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07/13/2004
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Application #:
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09363605
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Filing Dt:
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07/29/1999
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Title:
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CAPTURING READ DATA
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09363789
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Filing Dt:
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07/29/1999
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Publication #:
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Pub Dt:
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04/11/2002
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Title:
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STORING A FLUSHED CACHE LINE IN A MEMORY BUFFER OF A CONTROLLER
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09363790
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Filing Dt:
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07/29/1999
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Title:
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ADJUSTING AND MEASURING THE TIMING OF A DATA STROBE SIGNAL WITH A FIRST DELAY LINE AND THROUGH ADDITIONAL DELAY LINE ADAPTED TO RECEIVE PULSE SIGNAL
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09378560
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Filing Dt:
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08/19/1999
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Title:
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APPARATUS AND METHOD FOR AUTOMATICALLY SELECTING AN APPROPRIATE SIGNAL FROM A PLURALITY OF SIGNALS, BASED ON THE CONFIGURATION OF A PERIPHERAL INSTALLED WITHIN A COMPUTING DEVICE
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09383169
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Filing Dt:
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08/25/1999
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Title:
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METHOD FOR TESTING A CONTROLLER WITH RANDOM CONSTRAINTS
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09383468
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Filing Dt:
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08/26/1999
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Title:
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MEMORY CACHE WITH SEQUENTIAL PAGE INDICATORS
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09384665
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Filing Dt:
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08/27/1999
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Title:
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ENHANCED BUS CONNECTIVITY THROUGH DISTRIBUTED LOADING
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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09386808
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Filing Dt:
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08/31/1999
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Publication #:
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Pub Dt:
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05/01/2003
| | | | |
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Title:
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BUS TO SYSTEM MEMORY DELAYED READ PROCESSING
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09386973
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Filing Dt:
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08/31/1999
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Title:
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MEMORY BANDWIDTH ALLOCATION BASED ON ACCESS COUNT PRIORITY SCHEME
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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09409367
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Filing Dt:
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09/30/1999
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Title:
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METHOD AND APPARATUS FOR AN ADJUSTABLE DELAY CIRCUIT HAVING ARRANGED SERIALLY COARSE STAGES RECEIVED BY A FINE DELAY STAGE
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09409523
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Filing Dt:
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09/30/1999
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Title:
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METHOD AND APPARATUS TO REDUCE MEMORY READ LATENCY
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09417964
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Filing Dt:
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10/13/1999
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Title:
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METHOD AND APPARATUS FOR PROVIDING VISIBILITY AND CONTROL OVER COMPONENTS WITHIN A PROGRAMMABLE LOGIC CIRCUIT FOR EMULATION PURPOSES
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09418465
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Filing Dt:
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10/15/1999
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Title:
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APPARATUS FOR FLEXIBLY ALLOCATING REQUEST/GRANT PINS BETWEEN MULTIPLE BUS CONTROLLERS
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09418466
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Filing Dt:
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10/15/1999
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Title:
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METHOD FOR PRESERVING MEMORY REQUEST ORDERING ACROSS MULTIPLE MEMORY CONTROLLERS
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09418467
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Filing Dt:
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10/15/1999
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Title:
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APPARATUS FOR PRESERVING MEMORY REQUEST ORDERING ACROSS MULTIPLE MEMORY CONTROLLERS
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Patent #:
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Issue Dt:
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05/07/2002
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Application #:
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09418468
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Filing Dt:
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10/15/1999
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Title:
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METHOD FOR FLEXIBLY ALLOCATING REQUEST/GRANT PINS BETWEEN MULTIPLE BUS CONTROLLERS
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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09432687
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Filing Dt:
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11/03/1999
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Publication #:
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Pub Dt:
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11/15/2001
| | | | |
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Title:
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METHOD AND DEVICE TO USE MEMORY ACCESS REQUEST TAGS
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09490771
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Filing Dt:
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01/24/2000
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Title:
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COMPUTER SYSTEM HAVING REDUCED NUMBER OF BUS BRIDGE TERMINALS
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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09493441
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Filing Dt:
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01/18/2000
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Title:
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METHOD OF INITIALIZING A PROCESSOR AND COMPUTER SYSTEM
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