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Reel/Frame:022092/0572   Pages: 6
Recorded: 01/13/2009
Attorney Dkt #:E8280.0062
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 25
1
Patent #:
7615390
Issue Dt:
11/10/2009
Application #:
10530063
Filing Dt:
03/31/2005
Publication #:
US20060040477
Pub Dt:
02/23/2006
Title:
METHOD AND APPARATUS FOR FORMING EXPITAXIAL LAYERS
2
Patent #:
7605060
Issue Dt:
10/20/2009
Application #:
10550853
Filing Dt:
09/22/2005
Publication #:
US20060205185
Pub Dt:
09/14/2006
Title:
METHOD OF EPITAXIAL DEOPOSITION OF AN N-DOPED SILICON LAYER
3
Patent #:
6906400
Issue Dt:
06/14/2005
Application #:
10756840
Filing Dt:
01/13/2004
Publication #:
US20040227158
Pub Dt:
11/18/2004
Title:
SIGE STRAIN RELAXED BUFFER FOR HIGH MOBILITY DEVICES AND A METHOD OF FABRICATING IT
4
Patent #:
7189648
Issue Dt:
03/13/2007
Application #:
10966141
Filing Dt:
10/15/2004
Publication #:
US20050112875
Pub Dt:
05/26/2005
Title:
METHOD FOR REDUCING THE CONTACT RESISTANCE OF THE CONNECTION REGIONS OF A SEMICONDUCTOR DEVICE
5
Patent #:
7214592
Issue Dt:
05/08/2007
Application #:
10966145
Filing Dt:
10/15/2004
Publication #:
US20050112831
Pub Dt:
05/26/2005
Title:
METHOD AND APPARATUS FOR FORMING A SEMICONDUCTOR SUBSTRATE WITH A LAYER STRUCTURE OF ACTIVATED DOPANTS
6
Patent #:
7157356
Issue Dt:
01/02/2007
Application #:
10966152
Filing Dt:
10/15/2004
Publication #:
US20050127436
Pub Dt:
06/16/2005
Title:
METHOD FOR FORMING A NOTCHED GATE INSULATOR FOR ADVANCED MIS SEMICONDUCTOR DEVICES AND DEVICES THUS OBTAINED
7
Patent #:
7238625
Issue Dt:
07/03/2007
Application #:
10966153
Filing Dt:
10/15/2004
Publication #:
US20050130377
Pub Dt:
06/16/2005
Title:
METHOD FOR PROCESSING A SEMICONDUCTOR DEVICE COMPRISING A SILICON-OXY-NITRIDE DIELECTRIC LAYER
8
Patent #:
7226827
Issue Dt:
06/05/2007
Application #:
10978786
Filing Dt:
10/18/2004
Publication #:
US20050145943
Pub Dt:
07/07/2005
Title:
METHOD FOR FABRICATING SEMICONDUCTOR DEVICES HAVING SILICIDED ELECTRODES
9
Patent #:
7326620
Issue Dt:
02/05/2008
Application #:
11077973
Filing Dt:
03/11/2005
Publication #:
US20050236663
Pub Dt:
10/27/2005
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINABLE WITH SUCH A METHOD
10
Patent #:
7361453
Issue Dt:
04/22/2008
Application #:
11081797
Filing Dt:
03/15/2005
Publication #:
US20050214690
Pub Dt:
09/29/2005
Title:
METHOD FOR CREATING A PATTERN IN A MATERIAL AND SEMICONDUCTOR STRUCTURE PROCESSED THEREWITH
11
Patent #:
7122452
Issue Dt:
10/17/2006
Application #:
11081798
Filing Dt:
03/15/2005
Publication #:
US20050227421
Pub Dt:
10/13/2005
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR ON A SILICON ON INSULATOR (SOI) SUBSTRATE USING SOLID EPITAXIAL REGROWTH (SPER) AND SEMICONDUCTOR DEVICE MADE THEREBY
12
Patent #:
7510959
Issue Dt:
03/31/2009
Application #:
11083344
Filing Dt:
03/16/2005
Publication #:
US20050215047
Pub Dt:
09/29/2005
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING DAMASCENE STRUCTURES WITH AIR GAPS
13
Patent #:
7488669
Issue Dt:
02/10/2009
Application #:
11083356
Filing Dt:
03/16/2005
Publication #:
US20050214985
Pub Dt:
09/29/2005
Title:
METHOD TO MAKE MARKERS FOR DOUBLE GATE SOI PROCESSING
14
Patent #:
7589425
Issue Dt:
09/15/2009
Application #:
11084081
Filing Dt:
03/17/2005
Publication #:
US20050221600
Pub Dt:
10/06/2005
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING DAMASCENE STRUCTURES WITH AIR GAPS
15
Patent #:
7795112
Issue Dt:
09/14/2010
Application #:
11093265
Filing Dt:
03/28/2005
Publication #:
US20050227444
Pub Dt:
10/13/2005
Title:
METHOD OF FABRICATING SELF-ALIGNED SOURCE AND DRAIN CONTACTS IN A DOUBLE GATE FET WITH CONTROLLED MANUFACTURING OF A THIN SI OR NON-SI CHANNEL
16
Patent #:
NONE
Issue Dt:
Application #:
11382986
Filing Dt:
05/12/2006
Publication #:
US20060263961
Pub Dt:
11/23/2006
Title:
Method for Forming Dual Fully Silicided Gates and Devices with Dual Fully Silicided Gates
17
Patent #:
7491635
Issue Dt:
02/17/2009
Application #:
11484439
Filing Dt:
07/11/2006
Publication #:
US20070015334
Pub Dt:
01/18/2007
Title:
METHOD FOR FORMING A FULLY SILICIDED GATE AND DEVICES OBTAINED THEREOF
18
Patent #:
7320939
Issue Dt:
01/22/2008
Application #:
11526116
Filing Dt:
09/22/2006
Publication #:
US20070020930
Pub Dt:
01/25/2007
Title:
SEMICONDUCTOR DEVICE FABRICATED BY A METHOD OF REDUCING THE CONTACT RESISTANCE OF THE CONNECTION REGIONS
19
Patent #:
NONE
Issue Dt:
Application #:
11636817
Filing Dt:
12/11/2006
Publication #:
US20070155118
Pub Dt:
07/05/2007
Title:
Method for forming a notched gate insulator for advanced MIS semiconductor devices and devices thus obtained
20
Patent #:
7948543
Issue Dt:
05/24/2011
Application #:
11745302
Filing Dt:
05/07/2007
Publication #:
US20070206207
Pub Dt:
09/06/2007
Title:
IMAGING APPARATUS PROVIDED WITH IMAGE SCALING FUNCTION AND IMAGE DATA THINNING-OUT READOUT FUNCTION
21
Patent #:
NONE
Issue Dt:
Application #:
11750916
Filing Dt:
05/18/2007
Publication #:
US20070215951
Pub Dt:
09/20/2007
Title:
SEMICONDUCTOR DEVICES HAVING SILICIDED ELECTRODES
22
Patent #:
NONE
Issue Dt:
Application #:
11830735
Filing Dt:
07/30/2007
Publication #:
US20080057685
Pub Dt:
03/06/2008
Title:
METHOD FOR FORMING DOPED METAL-SEMICONDUCTOR COMPOUND REGIONS
23
Patent #:
7582547
Issue Dt:
09/01/2009
Application #:
11833931
Filing Dt:
08/03/2007
Publication #:
US20080057683
Pub Dt:
03/06/2008
Title:
METHOD FOR JUNCTION FORMATION IN A SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE MADE THEREOF
24
Patent #:
7897952
Issue Dt:
03/01/2011
Application #:
11914638
Filing Dt:
09/23/2009
Publication #:
US20100001248
Pub Dt:
01/07/2010
Title:
PHASE-CHANGE MEMORY CELL WITH A PATTERNED LAYER
25
Patent #:
8008644
Issue Dt:
08/30/2011
Application #:
11914645
Filing Dt:
07/10/2008
Publication #:
US20080265237
Pub Dt:
10/30/2008
Title:
PHASE-CHANGE MEMORY CELL HAVING TWO INSULATED REGIONS
Assignor
1
KONINKLIJKE PHILIPS ELECTRONICS N.V.
Exec Dt:
11/25/2008
Assignee
1
NXP B.V.
HIGH TECH CAMPUS 60
5656 AG EINDHOVEN, NETHERLANDS
Correspondence name and address
DICKSTEIN SHAPIRO LLP
1825 EYE STREET, NW
WASHINGTON, DC 20006

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