Total properties:
35
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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09465880
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Filing Dt:
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12/16/1999
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Title:
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METHOD AND APPARATUS FOR THICKNESS CONTROL AND REPRODUCIBILITY OF DIELECTRIC FILM DEPOSITION
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10072458
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Filing Dt:
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02/07/2002
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Publication #:
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Pub Dt:
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08/22/2002
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Title:
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SYSTEM FOR RAPID CONFIGURATION OF A PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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10072461
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Filing Dt:
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02/07/2002
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Publication #:
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Pub Dt:
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08/22/2002
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Title:
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PROGRAMMABLE LOGIC DEVICE INCLUDING BI-DIRECTIONAL SHIFT REGISTER
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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10145390
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Filing Dt:
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05/14/2002
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Publication #:
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Pub Dt:
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11/28/2002
| | | | |
Title:
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CONCURRENT LOGIC OPERATIONS USING DECODER CIRCUITRY OF A LOOK-UP TABLE
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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10172355
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Filing Dt:
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06/14/2002
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Publication #:
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Pub Dt:
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12/19/2002
| | | | |
Title:
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METHOD FOR SHARING CONFIGURATION DATA FOR HIGH LOGIC DENSITY ON CHIP
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10186346
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Filing Dt:
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06/28/2002
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Publication #:
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Pub Dt:
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01/02/2003
| | | | |
Title:
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FIELD PROGRAMMABLE LOGIC DEVICE WITH EFFICIENT MEMORY UTILIZATION
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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10269166
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Filing Dt:
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10/10/2002
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Publication #:
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Pub Dt:
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04/15/2004
| | | | |
Title:
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DECODER SCHEME FOR MAKING LARGE SIZE DECODER
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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10319436
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Filing Dt:
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12/13/2002
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Publication #:
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Pub Dt:
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07/31/2003
| | | | |
Title:
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RAPID PARTIAL CONFIGURATION OF RECONFIGURABLE DEVICES
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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10347139
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Filing Dt:
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01/17/2003
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Publication #:
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Pub Dt:
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09/11/2003
| | | | |
Title:
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UTILIZATION OF UNUSED IO BLOCK FOR CORE LOGIC FUNCTIONS
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Patent #:
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Issue Dt:
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04/12/2005
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Application #:
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10407801
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Filing Dt:
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04/04/2003
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Publication #:
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Pub Dt:
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11/27/2003
| | | | |
Title:
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LOW POWER CLOCK DISTRIBUTION SCHEME
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Patent #:
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Issue Dt:
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12/26/2006
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Application #:
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10407802
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Filing Dt:
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04/04/2003
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Publication #:
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Pub Dt:
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11/20/2003
| | | | |
Title:
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ARCHITECTURE FOR PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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01/23/2007
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Application #:
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10436895
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Filing Dt:
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05/13/2003
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Publication #:
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Pub Dt:
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01/22/2004
| | | | |
Title:
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METHOD AND DEVICE FOR TESTING CONFIGURATION MEMORY CELLS IN PROGRAMMABLE LOGIC DEVICES (PLDS)
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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10460040
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Filing Dt:
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06/10/2003
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Publication #:
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Pub Dt:
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12/25/2003
| | | | |
Title:
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PLDS PROVIDING REDUCED DELAYS IN CASCADE CHAIN CIRCUITS
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Patent #:
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Issue Dt:
|
05/03/2005
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Application #:
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10464420
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Filing Dt:
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06/17/2003
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Publication #:
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Pub Dt:
|
02/26/2004
| | | | |
Title:
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FPGA PERIPHERAL ROUTING WITH SYMMETRIC EDGE TERMINATION AT FPGA BOUNDARIES
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Patent #:
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Issue Dt:
|
03/29/2005
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Application #:
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10608854
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Filing Dt:
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06/27/2003
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Publication #:
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Pub Dt:
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04/15/2004
| | | | |
Title:
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PROGRAMMABLE LOGIC DEVICES HAVING ENHANCED CASCADE FUNCTIONS TO PROVIDE INCREASED FLEXIBILITY
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Patent #:
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|
Issue Dt:
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03/25/2008
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Application #:
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10667199
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Filing Dt:
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09/18/2003
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Publication #:
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Pub Dt:
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08/05/2004
| | | | |
Title:
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METHOD AND APPARATUS OF RELOADING ERRONEOUS CONFIGURATION DATA FRAMES DURING CONFIGURATION OF PROGRAMMABLE LOGIC DEVICES
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Patent #:
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Issue Dt:
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10/17/2006
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Application #:
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10675908
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Filing Dt:
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09/29/2003
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Publication #:
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|
Pub Dt:
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07/08/2004
| | | | |
Title:
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MAPPING OF PROGRAMMABLE LOGIC DEVICES
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|
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Patent #:
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|
Issue Dt:
|
05/17/2005
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Application #:
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10684076
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Filing Dt:
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10/10/2003
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Publication #:
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Pub Dt:
|
07/08/2004
| | | | |
Title:
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SENSE AMPLIFIER WITH FEEDBACK-CONTROLLED BITLINE ACCESS
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Patent #:
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|
Issue Dt:
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04/18/2006
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Application #:
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10739395
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Filing Dt:
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12/18/2003
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Publication #:
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Pub Dt:
|
09/16/2004
| | | | |
Title:
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HIGH PERFORMANCE INTERCONNECT ARCHITECTURE FOR FIELD PROGRAMMABLE GATE ARRAYS
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|
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Patent #:
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|
Issue Dt:
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07/18/2006
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Application #:
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10830854
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Filing Dt:
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04/23/2004
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Publication #:
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|
Pub Dt:
|
02/17/2005
| | | | |
Title:
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PROGRAMMABLE LOGIC DEVICE WITH REDUCED POWER CONSUMPTION
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|
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Patent #:
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|
Issue Dt:
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03/13/2007
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Application #:
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10830862
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Filing Dt:
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04/23/2004
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Publication #:
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Pub Dt:
|
02/17/2005
| | | | |
Title:
|
METHOD FOR MAPPING A LOGIC CIRCUIT TO A PROGRAMMABLE LOOK UP TABLE (LUT)
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Patent #:
|
|
Issue Dt:
|
01/02/2007
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Application #:
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10954981
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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06/16/2005
| | | | |
Title:
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METHOD AND DEVICE FOR CONFIGURATION OF PLDS
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|
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Patent #:
|
|
Issue Dt:
|
10/20/2009
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Application #:
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11005247
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Filing Dt:
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12/06/2004
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Publication #:
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|
Pub Dt:
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08/04/2005
| | | | |
Title:
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PROGRAMMABLE LOGIC DEVICES
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|
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Patent #:
|
|
Issue Dt:
|
08/19/2008
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Application #:
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11025785
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Filing Dt:
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12/29/2004
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Publication #:
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|
Pub Dt:
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07/21/2005
| | | | |
Title:
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OPTIMAL MAPPING OF LUT BASED FPGA
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|
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Patent #:
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|
Issue Dt:
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09/30/2008
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Application #:
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11027292
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Filing Dt:
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12/30/2004
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Publication #:
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Pub Dt:
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08/11/2005
| | | | |
Title:
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AN IMPROVED SYSTEM FOR DELAY REDUCTION DURING TECHNOLOGY MAPPING IN FPGA
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Patent #:
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|
Issue Dt:
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09/18/2007
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Application #:
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11190509
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Filing Dt:
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07/26/2005
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Publication #:
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|
Pub Dt:
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02/02/2006
| | | | |
Title:
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FPGA-BASED DIGITAL CIRCUIT FOR REDUCING READBACK TIME
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Patent #:
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|
Issue Dt:
|
02/07/2012
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Application #:
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11238123
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Filing Dt:
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09/28/2005
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Publication #:
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Pub Dt:
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04/06/2006
| | | | |
Title:
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FIELD PROGRAMMABLE GATE ARRAY
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Patent #:
|
|
Issue Dt:
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03/27/2007
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Application #:
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11254558
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Filing Dt:
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10/20/2005
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Publication #:
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Pub Dt:
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06/08/2006
| | | | |
Title:
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CONFIGURATION MEMORY STRUCTURE
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|
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Patent #:
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|
Issue Dt:
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12/11/2007
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Application #:
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11258616
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Filing Dt:
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10/25/2005
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Publication #:
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Pub Dt:
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06/29/2006
| | | | |
Title:
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INTERCONNECT STRUCTURE ENABLING INDIRECT ROUTING IN PROGRAMMABLE LOGIC
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|
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Patent #:
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|
Issue Dt:
|
07/06/2010
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Application #:
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11261420
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Filing Dt:
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10/27/2005
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Publication #:
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Pub Dt:
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04/27/2006
| | | | |
Title:
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INTERCONNECT STRUCTURE AND METHOD IN PROGRAMMABLE DEVICES
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Patent #:
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|
Issue Dt:
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05/13/2008
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Application #:
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11263386
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Filing Dt:
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10/31/2005
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Publication #:
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|
Pub Dt:
|
05/04/2006
| | | | |
Title:
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CONFIGURABLE LOGIC DEVICE PROVIDING ENHANCED FLEXIBILITY, SCALABILITY AND PROVIDING AREA EFFICIENT IMPLEMENTATION OF ARITHMETIC OPERATION ON N-BIT VARIABLES
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|
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Patent #:
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|
Issue Dt:
|
07/13/2010
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Application #:
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11264674
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Filing Dt:
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11/01/2005
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Publication #:
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Pub Dt:
|
06/08/2006
| | | | |
Title:
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FPGA HAVING A DIRECT ROUTING STRUCTURE
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|
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Patent #:
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|
Issue Dt:
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01/13/2009
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Application #:
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11294645
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Filing Dt:
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12/05/2005
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Publication #:
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|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
RAPID INTERCONNECT AND LOGIC TESTING OF FPGA DEVICE
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|
Patent #:
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|
Issue Dt:
|
08/17/2010
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Application #:
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11318347
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Filing Dt:
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12/23/2005
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Publication #:
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Pub Dt:
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01/11/2007
| | | | |
Title:
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SELF TEST STRUCTURE FOR INTERCONNECT AND LOGIC ELEMENT TESTING IN PROGRAMMABLE DEVICES
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Patent #:
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Issue Dt:
|
03/09/2010
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Application #:
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11319015
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Filing Dt:
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12/27/2005
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Publication #:
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Pub Dt:
|
08/24/2006
| | | | |
Title:
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EFFICIENT METHOD FOR MAPPING A LOGIC DESIGN ON FIELD PROGRAMMABLE GATE ARRAYS
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|