Patent Assignment Details
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Reel/Frame: | 010177/0576 | |
| Pages: | 4 |
| | Recorded: | 08/13/1999 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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09373636
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Filing Dt:
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08/13/1999
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Title:
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A METHOD FOR MAKING IMPROVED POLYSILICON FET GATE ELECTRODES HAVING COMPOSITE SIDEWALL SPACERS USING A TRAPEZOIDAL-SHAPED INSULATING LAYER FOR MORE RELIABLE INTEGRATED CIRCUITS
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Assignee
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121 PARK AVE. 3, SCIENCE-BASED INDUSTRIAL PARK |
HSIN-CHU, TAIWAN R.O.C |
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Correspondence name and address
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GEORGE O. SAILE
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20 MCINTOSH DRIVE
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POUGHKEEPSIE, NY 12603
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