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Reel/Frame:023627/0576   Pages: 12
Recorded: 12/10/2009
Attorney Dkt #:MICRON ASSIGNMENTS
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 50
1
Patent #:
5734620
Issue Dt:
03/31/1998
Application #:
08661810
Filing Dt:
06/11/1996
Title:
HIERARCHICAL MEMORY ARRAY STRUCTURE WITH REDUNDANT COMPONENTS HAVING ELECTRICALLY ISOLATED BIT LINES
2
Patent #:
5818780
Issue Dt:
10/06/1998
Application #:
08717170
Filing Dt:
09/20/1996
Title:
MEMORY DEVICE WITH DISTRIBUTED VOLTAGE REGULATION SYSTEM
3
Patent #:
5677573
Issue Dt:
10/14/1997
Application #:
08743502
Filing Dt:
11/04/1996
Title:
A FIELD EFFECT TRANSISTOR
4
Patent #:
5724301
Issue Dt:
03/03/1998
Application #:
08752578
Filing Dt:
11/21/1996
Title:
HIERARCHICAL MEMORY ARRAY STRUCTURE HAVING ELECTRICALLY ISOLATED BIT LINES FOR TEMPORARY DATA STORAGE
5
Patent #:
5838620
Issue Dt:
11/17/1998
Application #:
08796148
Filing Dt:
02/06/1997
Title:
CIRCUIT FOR CANCELING AND REPLACING REDUNDANT ELEMENTS
6
Patent #:
5946244
Issue Dt:
08/31/1999
Application #:
08811918
Filing Dt:
03/05/1997
Title:
DELAY-LOCKED LOOP WITH BINARY-COUPLED CAPACITOR
7
Patent #:
5677884
Issue Dt:
10/14/1997
Application #:
08816203
Filing Dt:
02/28/1997
Title:
CIRCUIT FOR CANCELLING AND REPLACING REDUNDANT ELEMENTS
8
Patent #:
6057200
Issue Dt:
05/02/2000
Application #:
08831360
Filing Dt:
04/01/1997
Title:
METHOD OF MAKING A FIELD EFFECT TRANSISTOR HAVING AN ELEVATED SOURCE AND AN ELEVATED DRAIN
9
Patent #:
5831334
Issue Dt:
11/03/1998
Application #:
08912899
Filing Dt:
08/15/1997
Title:
FIELD EFFECT TRANSISTOR COMPRISING ELECTRICALLY CONDUCTIVE PLUGS HAVING MONOCRYSTALLINE AND POLYCRYSTALLINE SILICON
10
Patent #:
5913128
Issue Dt:
06/15/1999
Application #:
08959648
Filing Dt:
10/28/1997
Title:
METHOD FOR FORMING TEXTURIZED POLYSILICON
11
Patent #:
5912579
Issue Dt:
06/15/1999
Application #:
09133586
Filing Dt:
08/13/1998
Title:
CIRCUIT FOR CANCELLING AND REPLACING REDUNDANT ELEMENTS
12
Patent #:
6208568
Issue Dt:
03/27/2001
Application #:
09133714
Filing Dt:
08/13/1998
Title:
CIRCUIT FOR CANCELLING AND REPLACING REDUNDANT ELEMENTS
13
Patent #:
6238955
Issue Dt:
05/29/2001
Application #:
09135377
Filing Dt:
08/17/1998
Title:
INTEGRATED CIRCUITRY FUSE FORMING METHODS, INTEGRATED CIRCUITRY PROGRAMMING METHODS, AND RELATED INTEGRATED CIRCUITRY
14
Patent #:
6249037
Issue Dt:
06/19/2001
Application #:
09135392
Filing Dt:
08/17/1998
Title:
INTEGRATED CIRCUITRY FUSE FORMING METHODS, INTEGRATED CIRCUITRY PROGRAMMING METHODS, AND RELATED INTEGRATED CIRCUITRY
15
Patent #:
5998844
Issue Dt:
12/07/1999
Application #:
09153088
Filing Dt:
09/14/1998
Title:
SEMICONDUCTOR CONSTRUCTUIONS COMPRISING ELECTRICALLY CONDUCTIVE PLUGS HAVING MONOCRYSTALLINE AND POLYCRYSTALLINE SILICON
16
Patent #:
6009034
Issue Dt:
12/28/1999
Application #:
09167042
Filing Dt:
10/05/1998
Title:
MEMORY DEVICE WITH DISTRIBUTED VOLTAGE REGULATION SYSTEM
17
Patent #:
6400641
Issue Dt:
06/04/2002
Application #:
09353571
Filing Dt:
07/15/1999
Title:
DELAY-LOCKED LOOP WITH BINARY-COUPLED CAPACITOR
18
Patent #:
6141276
Issue Dt:
10/31/2000
Application #:
09389680
Filing Dt:
09/02/1999
Title:
APPARATUS AND METHOD FOR INCREASING TEST FLEXIBILITY OF A MEMORY DEVICE
19
Patent #:
6300170
Issue Dt:
10/09/2001
Application #:
09393548
Filing Dt:
09/10/1999
Title:
INTEGRATED CIRCUITRY FUSE FORMING METHODS, INTEGRATED CIRCUITRY PROGRAMMING METHODS, AND RELATED INTEGRATED CIRCUITRY
20
Patent #:
6307802
Issue Dt:
10/23/2001
Application #:
09454532
Filing Dt:
12/06/1999
Title:
MEMORY DEVICE WITH DISTRIBUTED VOLTAGE REGULATION SYSTEM
21
Patent #:
6265299
Issue Dt:
07/24/2001
Application #:
09556245
Filing Dt:
04/24/2000
Title:
Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry
22
Patent #:
6262921
Issue Dt:
07/17/2001
Application #:
09570241
Filing Dt:
05/12/2000
Title:
Delay-locked loop with binary-coupled capacitor
23
Patent #:
6256259
Issue Dt:
07/03/2001
Application #:
09570242
Filing Dt:
05/12/2000
Title:
Delay-locked loop with binary-coupled capacitor
24
Patent #:
6333887
Issue Dt:
12/25/2001
Application #:
09596966
Filing Dt:
06/20/2000
Title:
Circuits and methods for selectively coupling redundant elements into an integrated circuit
25
Patent #:
6459635
Issue Dt:
10/01/2002
Application #:
09703360
Filing Dt:
10/31/2000
Title:
APPARATUS AND METHOD FOR INCREASING TEST FLEXIBILITY OF A MEMORY DEVICE
26
Patent #:
6388284
Issue Dt:
05/14/2002
Application #:
09754924
Filing Dt:
01/03/2001
Publication #:
US20010001210
Pub Dt:
05/17/2001
Title:
CAPACITOR STRUCTURES
27
Patent #:
6571352
Issue Dt:
05/27/2003
Application #:
09796080
Filing Dt:
02/28/2001
Publication #:
US20010044916
Pub Dt:
11/22/2001
Title:
DEVICE AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY
28
Patent #:
6680519
Issue Dt:
01/20/2004
Application #:
09844059
Filing Dt:
04/26/2001
Publication #:
US20010015471
Pub Dt:
08/23/2001
Title:
INTEGRATED CIRCUITRY FUSE FORMING METHODS, INTEGRATED CIRCUITRY PROGRAMMING METHODS, AND RELATED INTEGRATED CIRCUITRY
29
Patent #:
6483757
Issue Dt:
11/19/2002
Application #:
09895503
Filing Dt:
06/29/2001
Publication #:
US20020008556
Pub Dt:
01/24/2002
Title:
DELAY-LOCKED LOOP WITH BINARY-COUPLED CAPACITOR
30
Patent #:
6490224
Issue Dt:
12/03/2002
Application #:
09907316
Filing Dt:
07/16/2001
Publication #:
US20010053100
Pub Dt:
12/20/2001
Title:
DELAY-LOCKED LOOP WITH BINARY-COUPLED CAPACITOR
31
Patent #:
6607944
Issue Dt:
08/19/2003
Application #:
09918345
Filing Dt:
07/30/2001
Title:
METHOD OF MAKING MEMORY CELL ARRAYS
32
Patent #:
6442084
Issue Dt:
08/27/2002
Application #:
09928404
Filing Dt:
08/14/2001
Publication #:
US20010053101
Pub Dt:
12/20/2001
Title:
SEMICONDUCTOR MEMORY HAVING SEGMENTED ROW REPAIR
33
Patent #:
6910152
Issue Dt:
06/21/2005
Application #:
09932403
Filing Dt:
08/17/2001
Publication #:
US20020019961
Pub Dt:
02/14/2002
Title:
DEVICE AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY
34
Patent #:
6490207
Issue Dt:
12/03/2002
Application #:
10033574
Filing Dt:
11/02/2001
Publication #:
US20020057624
Pub Dt:
05/16/2002
Title:
DELAY-LOCKED LOOP WITH BINARY-COUPLED CAPACITOR
35
Patent #:
7045834
Issue Dt:
05/16/2006
Application #:
10059727
Filing Dt:
01/29/2002
Publication #:
US20030102515
Pub Dt:
06/05/2003
Title:
MEMORY CELL ARRAYS
36
Patent #:
6577523
Issue Dt:
06/10/2003
Application #:
10121805
Filing Dt:
04/12/2002
Publication #:
US20020110015
Pub Dt:
08/15/2002
Title:
REDUCED AREA SENSE AMPLIFIER ISOLATION LAYOUT IN A DYNAMIC RAM ARCHITECTURE
37
Patent #:
6600671
Issue Dt:
07/29/2003
Application #:
10225908
Filing Dt:
08/21/2002
Publication #:
US20020191461
Pub Dt:
12/19/2002
Title:
REDUCED AREA SENSE AMPLIFIER ISOLATION LAYOUT IN A DYNAMIC RAM ARCHITECTURE
38
Patent #:
6892318
Issue Dt:
05/10/2005
Application #:
10375994
Filing Dt:
02/27/2003
Publication #:
US20030154422
Pub Dt:
08/14/2003
Title:
METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY
39
Patent #:
6724663
Issue Dt:
04/20/2004
Application #:
10376936
Filing Dt:
02/28/2003
Publication #:
US20030179624
Pub Dt:
09/25/2003
Title:
ERASE BLOCK ARCHITECTURE FOR NON-VOLATILE MEMORY
40
Patent #:
6981100
Issue Dt:
12/27/2005
Application #:
10972324
Filing Dt:
10/26/2004
Publication #:
US20050083758
Pub Dt:
04/21/2005
Title:
SYNCHRONOUS DRAM WITH SELECTABLE INTERNAL PREFETCH SIZE
41
Patent #:
7467334
Issue Dt:
12/16/2008
Application #:
11108651
Filing Dt:
04/11/2005
Publication #:
US20050193241
Pub Dt:
09/01/2005
Title:
METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY
42
Patent #:
7154780
Issue Dt:
12/26/2006
Application #:
11206529
Filing Dt:
08/18/2005
Publication #:
US20050276130
Pub Dt:
12/15/2005
Title:
CONTIGUOUS BLOCK ADDRESSING SCHEME
43
Patent #:
7154781
Issue Dt:
12/26/2006
Application #:
11207017
Filing Dt:
08/18/2005
Publication #:
US20050276121
Pub Dt:
12/15/2005
Title:
CONTIGUOUS BLOCK ADDRESSING SCHEME
44
Patent #:
7154782
Issue Dt:
12/26/2006
Application #:
11207105
Filing Dt:
08/18/2005
Publication #:
US20050278481
Pub Dt:
12/15/2005
Title:
CONTIGUOUS BLOCK ADDRESSING SCHEME
45
Patent #:
7120754
Issue Dt:
10/10/2006
Application #:
11268760
Filing Dt:
11/08/2005
Publication #:
US20060112231
Pub Dt:
05/25/2006
Title:
SYNCHRONOUS DRAM WITH SELECTABLE INTERNAL PREFETCH SIZE
46
Patent #:
7170806
Issue Dt:
01/30/2007
Application #:
11367467
Filing Dt:
03/03/2006
Publication #:
US20060158944
Pub Dt:
07/20/2006
Title:
DATA PATH HAVING GROUNDED PRECHARGE OPERATION AND TEST COMPRESSION CAPABILITY
47
Patent #:
7120055
Issue Dt:
10/10/2006
Application #:
11367922
Filing Dt:
03/03/2006
Publication #:
US20060146611
Pub Dt:
07/06/2006
Title:
FLASH MEMORY DEVICE WITH IMPROVED PROGRAMMING PERFORMANCE
48
Patent #:
7280403
Issue Dt:
10/09/2007
Application #:
11522600
Filing Dt:
09/18/2006
Publication #:
US20070014158
Pub Dt:
01/18/2007
Title:
FLASH MEMORY DEVICE WITH IMPROVED PROGRAMMING PERFORMANCE
49
Patent #:
7908427
Issue Dt:
03/15/2011
Application #:
12387058
Filing Dt:
04/27/2009
Publication #:
US20100030949
Pub Dt:
02/04/2010
Title:
NON-VOLATILE MEMORY DEVICES AND CONTROL AND OPERATION THEREOF
50
Patent #:
7888261
Issue Dt:
02/15/2011
Application #:
12553691
Filing Dt:
09/03/2009
Publication #:
US20100197132
Pub Dt:
08/05/2010
Title:
BARRIER-METAL-FREE COPPER DAMASCENE TECHNOLOGY USING ATOMIC HYDROGEN ENHANCED REFLOW
Assignor
1
MICRON TECHNOLOGY INC.
Exec Dt:
04/02/2009
Assignee
1
MOSAID TECHNOLOGIES INCORPORATED
11 HINES ROAD
SUITE 203
OTTAWA, CANADA K2K 2X1
Correspondence name and address
MOSAID TECHNOLOGIES INCORPORATED
11HINES ROAD
SUITE 203
OTTAWA, K2K 2X1 CANADA

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