Total properties:
144
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2
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2
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Patent #:
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Issue Dt:
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11/25/2014
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Application #:
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14105419
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Filing Dt:
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12/13/2013
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Publication #:
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Pub Dt:
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05/01/2014
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Title:
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STSTEM AND METHOD FOR CONTROLLING BYPASS OF A VOLTAGE REGULATOR
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Patent #:
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Issue Dt:
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04/07/2015
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Application #:
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14108294
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Filing Dt:
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12/16/2013
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Title:
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ANALOG-TO-DIGITAL CONVERTER WITH CLOCK HALTING CIRCUIT
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14110877
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Filing Dt:
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10/09/2013
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Publication #:
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Pub Dt:
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02/06/2014
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Title:
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SYSTEM AND METHOD TO TEST A SEMICONDUCTOR POWER SWITCH
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14111571
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Filing Dt:
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10/14/2013
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Publication #:
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Pub Dt:
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02/06/2014
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Title:
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METHOD AND APPARATUS FOR GENERATING RESOURCE EFFICIENT COMPUTER PROGRAM CODE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14111572
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Filing Dt:
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10/14/2013
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Publication #:
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Pub Dt:
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02/06/2014
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Title:
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METHOD, COMPUTER PROGRAM PRODUCT, AND APPARATUS FOR SIMULATING ELECTROMAGNETIC IMMUNITY OF AN ELECTRONIC DEVICE
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Patent #:
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Issue Dt:
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09/01/2015
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Application #:
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14111775
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Filing Dt:
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10/15/2013
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Publication #:
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Pub Dt:
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02/06/2014
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Title:
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SYSTEM AND METHOD FOR CLOCK SIGNAL GENERATION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14111821
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Filing Dt:
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10/15/2013
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Publication #:
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Pub Dt:
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02/06/2014
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Title:
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ANTENNA DEVICE, AMPLIFIER AND RECEIVER CIRCUIT, AND RADAR CIRCUIT
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Patent #:
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Issue Dt:
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11/03/2015
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Application #:
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14112042
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Filing Dt:
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10/16/2013
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Publication #:
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Pub Dt:
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02/13/2014
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Title:
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METHOD AND DEVICE FOR DIAGNOSING A RESERVOIR CAPACITOR OF A VEHICLE PASSENGER PROTECTION SYSTEM, AND VEHICLE SAFETY SYSTEM INCORPORATING SUCH DEVICE
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Patent #:
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Issue Dt:
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08/25/2015
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Application #:
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14115210
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Filing Dt:
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11/01/2013
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Publication #:
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Pub Dt:
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03/27/2014
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Title:
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INTEGRATED CIRCUIT DEVICE AND METHOD OF ENABLING THERMAL REGULATION WITHIN AN INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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05/31/2016
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Application #:
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14115223
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Filing Dt:
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11/01/2013
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Publication #:
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Pub Dt:
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03/20/2014
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Title:
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VOLTAGE REGULATING CIRCUIT WITH SELECTABLE VOLTAGE REFERENCES AND METHOD THEREFOR
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14115710
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Filing Dt:
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11/05/2013
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Publication #:
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Pub Dt:
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03/20/2014
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Title:
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INTEGRATED CIRCUIT DEVICE AND METHOD FOR SELF-HEATING AN INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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07/07/2015
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Application #:
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14116785
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Filing Dt:
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11/11/2013
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Publication #:
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Pub Dt:
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06/26/2014
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Title:
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INTEGRATED CIRCUIT DEVICE, VOLTAGE REGULATOR MODULE AND METHOD FOR COMPENSATING A VOLTAGE SIGNAL
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Patent #:
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Issue Dt:
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02/10/2015
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Application #:
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14119364
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Filing Dt:
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11/21/2013
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Publication #:
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Pub Dt:
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04/03/2014
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Title:
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CIRCUIT ARRANGEMENT, LIGHTING APPARATUS AND METHOD OF CROSSTALK-COMPENSATED CURRENT SENSING
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14119372
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Filing Dt:
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11/21/2013
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Publication #:
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Pub Dt:
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03/27/2014
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Title:
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METHOD AND DEVICE FOR ENCODING AND DECODING AN IMAGE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14122523
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Filing Dt:
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11/26/2013
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Publication #:
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Pub Dt:
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04/24/2014
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Title:
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INTEGRATED CIRCUIT DEVICE AND METHOD FOR CONTROLLING AN OPERATING MODE OF AN ON-DIE MEMORY
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Patent #:
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Issue Dt:
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07/07/2015
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Application #:
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14122538
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Filing Dt:
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11/26/2013
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Publication #:
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Pub Dt:
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04/03/2014
| | | | |
Title:
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GROUND LOSS MONITORING CIRCUIT AND INTEGRATED CIRCUIT COMPRISING THE SAME
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Patent #:
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Issue Dt:
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08/09/2016
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Application #:
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14122556
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Filing Dt:
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11/26/2013
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Publication #:
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Pub Dt:
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04/10/2014
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Title:
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INTEGRATED CIRCUIT DEVICE AND METHOD OF IMPLEMENTING POWER GATING WITHIN AN INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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05/30/2017
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Application #:
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14125200
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Filing Dt:
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12/10/2013
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Publication #:
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Pub Dt:
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06/19/2014
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Title:
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PROCESSING APPARATUS AND METHOD OF SYNCHRONIZING A FIRST PROCESSING UNIT AND A SECOND PROCESSING UNIT
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Patent #:
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Issue Dt:
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09/20/2016
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Application #:
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14125203
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Filing Dt:
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12/10/2013
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Publication #:
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Pub Dt:
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04/10/2014
| | | | |
Title:
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INTEGRATED CIRCUIT DEVICE AND METHOD OF PERFORMING CUT-THROUGH FORWARDING OF PACKET DATA
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Patent #:
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Issue Dt:
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03/29/2016
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Application #:
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14132751
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Filing Dt:
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12/18/2013
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Publication #:
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Pub Dt:
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06/18/2015
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Title:
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LEVEL SHIFTER CIRCUIT
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Patent #:
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Issue Dt:
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05/22/2018
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Application #:
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14133217
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Filing Dt:
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12/18/2013
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Publication #:
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Pub Dt:
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06/18/2015
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Title:
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ION SENSITIVE FIELD EFFECT TRANSISTORS WITH PROTECTION DIODES AND METHODS OF THEIR FABRICATION
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Patent #:
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Issue Dt:
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10/03/2017
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Application #:
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14133551
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Filing Dt:
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12/18/2013
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Publication #:
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Pub Dt:
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06/18/2015
| | | | |
Title:
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METHODS FOR FORMING SEMICONDUCTOR DEVICES WITH STEPPED BOND PADS
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Patent #:
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Issue Dt:
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08/26/2014
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Application #:
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14133966
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Filing Dt:
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12/19/2013
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Publication #:
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Pub Dt:
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04/17/2014
| | | | |
Title:
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LATERALLY DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTORS HAVING A REDUCED SURFACE FIELD STRUCTURES
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Patent #:
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Issue Dt:
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02/16/2016
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Application #:
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14134082
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Filing Dt:
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12/19/2013
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Publication #:
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Pub Dt:
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06/25/2015
| | | | |
Title:
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LOW LEAKAGE CMOS CELL WITH LOW VOLTAGE SWING
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Patent #:
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|
Issue Dt:
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03/14/2017
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Application #:
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14134488
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Filing Dt:
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12/19/2013
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Publication #:
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Pub Dt:
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06/25/2015
| | | | |
Title:
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Analog Mixed Signal Model Equivalence Checking
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Patent #:
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Issue Dt:
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12/22/2015
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Application #:
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14135142
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Filing Dt:
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12/19/2013
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Publication #:
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Pub Dt:
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06/25/2015
| | | | |
Title:
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NON-VOLATILE MEMORY (NVM) CELL
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Patent #:
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Issue Dt:
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08/18/2015
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Application #:
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14135387
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Filing Dt:
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12/19/2013
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Publication #:
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Pub Dt:
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06/25/2015
| | | | |
Title:
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SYSTEM IN A PACKAGE (SiP)
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Patent #:
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Issue Dt:
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01/09/2018
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Application #:
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14135792
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Filing Dt:
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12/20/2013
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Publication #:
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Pub Dt:
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06/25/2015
| | | | |
Title:
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METHOD AND SYSTEM FOR AVOIDING NEW FLOW PACKET FLOOD FROM DATA PLANE TO CONTROL PLANE OF A NETWORK DEVICE
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Patent #:
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Issue Dt:
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01/10/2017
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Application #:
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14135956
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Filing Dt:
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12/20/2013
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Publication #:
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Pub Dt:
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06/25/2015
| | | | |
Title:
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MAGNETIC PRE-CONDITIONING OF MAGNETIC SENSORS
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Patent #:
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Issue Dt:
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04/14/2015
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Application #:
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14136057
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Filing Dt:
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12/20/2013
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Title:
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AUTOMATIC GENERATION OF VIA DEFINITIONS BASED ON MANUFACTURABILITY
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Patent #:
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Issue Dt:
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10/03/2017
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Application #:
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14136275
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Filing Dt:
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12/20/2013
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Publication #:
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Pub Dt:
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06/25/2015
| | | | |
Title:
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SEMICONDUCTOR DEVICES WITH INNER VIA
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14137530
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Filing Dt:
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12/20/2013
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Publication #:
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Pub Dt:
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06/25/2015
| | | | |
Title:
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SEMICONDUCTOR MANUFACTURING USING DESIGN VERIFICATION WITH MARKERS
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Patent #:
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Issue Dt:
|
04/14/2015
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Application #:
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14140123
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Filing Dt:
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12/24/2013
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Title:
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TRANSMITTER AND METHOD FOR REDUCING THE PEAK-TO-AVERAGE POWER RATIO OF A DIGITALLY MODULATED COMMUNICATION SIGNAL
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Patent #:
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|
Issue Dt:
|
03/22/2016
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Application #:
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14141458
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Filing Dt:
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12/27/2013
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Publication #:
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Pub Dt:
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07/02/2015
| | | | |
Title:
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HYBRID SYNCHRONOUS/ASYNCHRONOUS COUNTER
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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14141465
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Filing Dt:
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12/27/2013
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Publication #:
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Pub Dt:
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07/02/2015
| | | | |
Title:
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EMICONDUCTOR DEVICE WITH DIE TOP POWER CONNECTIONS
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Patent #:
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|
Issue Dt:
|
09/30/2014
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Application #:
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14141466
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Filing Dt:
|
12/27/2013
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Title:
|
WAVEFORM GENERATOR
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|
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Patent #:
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|
Issue Dt:
|
10/20/2015
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Application #:
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14141469
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Filing Dt:
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12/27/2013
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Publication #:
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Pub Dt:
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07/02/2015
| | | | |
Title:
|
CONFIGURABLE FLIP-FLOP CIRCUIT
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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14141471
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Filing Dt:
|
12/27/2013
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Publication #:
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Pub Dt:
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07/02/2015
| | | | |
Title:
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SEMICONDUCTOR WAFER DICING BLADE
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Patent #:
|
|
Issue Dt:
|
11/11/2014
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Application #:
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14141473
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Filing Dt:
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12/27/2013
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Title:
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TIMING PATH SLACK MONITORING SYSTEM
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Patent #:
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Issue Dt:
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11/17/2015
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Application #:
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14142924
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Filing Dt:
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12/30/2013
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Publication #:
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Pub Dt:
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09/11/2014
| | | | |
Title:
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LEAD FRAME AND SUBSTRATE SEMICONDUCTOR PACKAGE
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Patent #:
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Issue Dt:
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03/15/2016
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Application #:
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14144720
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Filing Dt:
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12/31/2013
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Publication #:
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Pub Dt:
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07/02/2015
| | | | |
Title:
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APPARATUS FABRICATION USING LOCALIZED ANNEALING
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Patent #:
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Issue Dt:
|
06/27/2017
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Application #:
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14144891
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Filing Dt:
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12/31/2013
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Publication #:
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Pub Dt:
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07/02/2015
| | | | |
Title:
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SYSTEM AND METHOD FOR LOW COST PATCHING OF HIGH VOLTAGE OPERATION MEMORY SPACE
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
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14144911
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Filing Dt:
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12/31/2013
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Publication #:
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Pub Dt:
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07/02/2015
| | | | |
Title:
|
METHODS AND APPARATUS FOR DISSIPATING HEAT FROM A DIE ASSEMBLY
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|
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Patent #:
|
|
Issue Dt:
|
02/16/2016
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Application #:
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14144919
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Filing Dt:
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12/31/2013
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Publication #:
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Pub Dt:
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07/02/2015
| | | | |
Title:
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IC PACKAGE WITH METAL INTERCONNECT STRUCTURE IMPLEMENTED BETWEEN METAL LAYERS OF DIE AND INTERPOSER
|
|