Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 026004/0585 | |
| Pages: | 6 |
| | Recorded: | 03/23/2011 | | |
Attorney Dkt #: | XA-9536,A,B,D,E,F |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09931860
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Filing Dt:
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08/20/2001
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Publication #:
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Pub Dt:
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02/21/2002
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Title:
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A METHOD OF CONTROLLING PAGE MODE ACCESS
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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09986347
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Filing Dt:
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11/08/2001
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Publication #:
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Pub Dt:
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03/21/2002
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Title:
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SEMICONDUCTOR DEVICE WITH AUTO ADDRESS ALLOCATION MEANS FOR A CACHE MEMORY
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09986348
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Filing Dt:
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11/08/2001
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Publication #:
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Pub Dt:
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05/02/2002
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Title:
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METHOD OF CONTROLLING PAGE MODE ACCESS
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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10712050
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Filing Dt:
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11/14/2003
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Publication #:
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Pub Dt:
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05/20/2004
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Title:
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MEMORY CONTROLLER AND DATA PROCESSING SYSTEM
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Patent #:
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Issue Dt:
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11/24/2009
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Application #:
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11453907
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Filing Dt:
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06/16/2006
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Publication #:
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Pub Dt:
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11/02/2006
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Title:
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MEMORY CONTROLLER AND DATA PROCESSING SYSTEM
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Patent #:
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Issue Dt:
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09/20/2011
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Application #:
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12620912
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Filing Dt:
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11/18/2009
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Publication #:
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Pub Dt:
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03/11/2010
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Title:
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MEMORY CONTROLLER AND DATA PROCESSING SYSTEM
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Assignee
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1753, SHIMONUMABE, NAKAHARA-KU, |
KAWASAKI-SHI, KANAGAWA, JAPAN |
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Correspondence name and address
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MITCHELL W. SHAPIRO
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1751 PINNACLE DRIVE, SUITE 500
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MCLEAN, VA 22102-3833
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