Total properties:
949
Page
6
of
10
Pages:
1 2 3 4 5 6 7 8 9 10
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2008
|
Application #:
|
11373133
|
Filing Dt:
|
03/13/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
OVERDRIVE PERIOD CONTROL DEVICE AND OVERDRIVE PERIOD DETERMINING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
11376169
|
Filing Dt:
|
03/16/2006
|
Publication #:
|
|
Pub Dt:
|
09/21/2006
| | | | |
Title:
|
SEMICONDUCTOR STORAGE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
11376297
|
Filing Dt:
|
03/16/2006
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE TEST METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
11389104
|
Filing Dt:
|
03/27/2006
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH DELAY SECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2009
|
Application #:
|
11392583
|
Filing Dt:
|
03/30/2006
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND TESTING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2008
|
Application #:
|
11399485
|
Filing Dt:
|
04/07/2006
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
DATA STORING METHOD OF DYNAMIC RAM AND SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2008
|
Application #:
|
11401889
|
Filing Dt:
|
04/12/2006
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
DUTY DETECTION CIRCUIT AND METHOD FOR CONTROLLING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
11409088
|
Filing Dt:
|
04/24/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
SEMICONDUCTOR STORAGE APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
11409097
|
Filing Dt:
|
04/24/2006
|
Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
|
SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR WRITING IN THE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
11418017
|
Filing Dt:
|
05/05/2006
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
NON-VOLATILE MULTI-LEVEL SEMICONDUCTOR FLASH MEMORY DEVICE AND METHOD OF DRIVING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11434715
|
Filing Dt:
|
05/17/2006
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
TERMINATION CIRCUIT AND SEMICONDUCTOR DEVICE COMPRISING THAT TERMINATION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
11443348
|
Filing Dt:
|
05/31/2006
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2008
|
Application #:
|
11465390
|
Filing Dt:
|
08/17/2006
|
Publication #:
|
|
Pub Dt:
|
05/10/2007
| | | | |
Title:
|
DUTY RATIO ADJUSTMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
11467793
|
Filing Dt:
|
08/28/2006
|
Publication #:
|
|
Pub Dt:
|
06/28/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH SUB-AMPLIFIERS HAVING A VARIABLE CURRENT SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
11495711
|
Filing Dt:
|
07/31/2006
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
Title:
|
INDUCTANCE ANALYSIS SYSTEM AND METHOD AND PROGRAM THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
11496578
|
Filing Dt:
|
08/01/2006
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
SEMICONDUCTOR-MEMORY DEVICE AND BANK REFRESH METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
11511438
|
Filing Dt:
|
08/29/2006
|
Publication #:
|
|
Pub Dt:
|
03/15/2007
| | | | |
Title:
|
METHOD FOR DESIGNING SEMICONDUCTOR APPARATUS, SYSTEM FOR AIDING TO DESIGN SEMICONDUCTOR APPARATUS, COMPUTER PROGRAM PRODUCT THEREFOR AND SEMICONDUCTOR PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
11512235
|
Filing Dt:
|
08/30/2006
|
Publication #:
|
|
Pub Dt:
|
05/10/2007
| | | | |
Title:
|
REDUNDANCY CIRCUIT AND SEMICONDUCTOR APPARATUS HAVING THE REDUNDANCY CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
11516701
|
Filing Dt:
|
09/07/2006
|
Publication #:
|
|
Pub Dt:
|
03/08/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2008
|
Application #:
|
11517315
|
Filing Dt:
|
09/08/2006
|
Publication #:
|
|
Pub Dt:
|
03/15/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH NO LATCH ERROR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
11522424
|
Filing Dt:
|
09/18/2006
|
Publication #:
|
|
Pub Dt:
|
04/19/2007
| | | | |
Title:
|
Data transfer operation completion detection circuit and semiconductor memory device provided therewith
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
11523705
|
Filing Dt:
|
09/20/2006
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
Title:
|
OUTPUT CONTROL SIGNAL GENERATING CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2008
|
Application #:
|
11539156
|
Filing Dt:
|
10/05/2006
|
Publication #:
|
|
Pub Dt:
|
04/10/2008
| | | | |
Title:
|
NROM MEMORY DEVICE WITH ENHANCED ENDURANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2008
|
Application #:
|
11543233
|
Filing Dt:
|
10/05/2006
|
Publication #:
|
|
Pub Dt:
|
04/05/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH LATENCY COUNTER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2009
|
Application #:
|
11543867
|
Filing Dt:
|
10/06/2006
|
Publication #:
|
|
Pub Dt:
|
04/12/2007
| | | | |
Title:
|
SEMICONDUCTOR STORAGE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
11544598
|
Filing Dt:
|
10/10/2006
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
Title:
|
DELAY CIRCUIT AND DELAY SYNCHRONIZATION LOOP DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
11544599
|
Filing Dt:
|
10/10/2006
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
Title:
|
DELAY CIRCUIT AND DELAY SYNCHRONIZATION LOOP DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
11554259
|
Filing Dt:
|
10/30/2006
|
Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
11560898
|
Filing Dt:
|
11/17/2006
|
Publication #:
|
|
Pub Dt:
|
05/24/2007
| | | | |
Title:
|
MEMORY BANK ARRANGEMENT FOR STACKED MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
11580111
|
Filing Dt:
|
10/13/2006
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
Title:
|
DELAY CIRCUIT AND DELAY SYNCHRONIZATION LOOP DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2009
|
Application #:
|
11580191
|
Filing Dt:
|
10/13/2006
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
VOLTAGE CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE VOLTAGE CONTROL CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2009
|
Application #:
|
11580895
|
Filing Dt:
|
10/16/2006
|
Publication #:
|
|
Pub Dt:
|
04/26/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE IN WHICH A MEMORY ARRAY IS REFRESHED BASED ON AN ADDRESS SIGNAL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2009
|
Application #:
|
11580902
|
Filing Dt:
|
10/16/2006
|
Publication #:
|
|
Pub Dt:
|
06/21/2007
| | | | |
Title:
|
CALIBRATION CIRCUIT AND SEMICONDUCTOR DEVICE INCORPORATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2010
|
Application #:
|
11581756
|
Filing Dt:
|
10/17/2006
|
Publication #:
|
|
Pub Dt:
|
04/19/2007
| | | | |
Title:
|
METHOD AND DESIGN SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT WITH A REDUCED PLACEMENT AREA
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
11582981
|
Filing Dt:
|
10/19/2006
|
Publication #:
|
|
Pub Dt:
|
05/10/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY CHIP WITH ON-DIE TERMINATION FUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
11583980
|
Filing Dt:
|
10/20/2006
|
Publication #:
|
|
Pub Dt:
|
04/26/2007
| | | | |
Title:
|
SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2009
|
Application #:
|
11584582
|
Filing Dt:
|
10/23/2006
|
Publication #:
|
|
Pub Dt:
|
04/26/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING TWO FUSES IN PARALLEL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
11585108
|
Filing Dt:
|
10/24/2006
|
Publication #:
|
|
Pub Dt:
|
06/28/2007
| | | | |
Title:
|
ZQ CALIBRATION CIRCUIT AND A SEMICONDUCTOR DEVICE INCLUDING A ZQ CALIBRATION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2009
|
Application #:
|
11585206
|
Filing Dt:
|
10/24/2006
|
Publication #:
|
|
Pub Dt:
|
06/14/2007
| | | | |
Title:
|
DLL CIRCUIT FEEDING BACK ZQ CALIBRATION RESULT, AND SEMICONDUCTOR DEVICE INCORPORATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
11585948
|
Filing Dt:
|
10/25/2006
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF ADJUSTING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
11586518
|
Filing Dt:
|
10/26/2006
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2008
|
Application #:
|
11588328
|
Filing Dt:
|
10/27/2006
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2008
|
Application #:
|
11589708
|
Filing Dt:
|
10/31/2006
|
Publication #:
|
|
Pub Dt:
|
11/01/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2008
|
Application #:
|
11598566
|
Filing Dt:
|
11/14/2006
|
Publication #:
|
|
Pub Dt:
|
05/31/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE HAVING DELAY CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
11598702
|
Filing Dt:
|
11/14/2006
|
Publication #:
|
|
Pub Dt:
|
03/29/2007
| | | | |
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
11599275
|
Filing Dt:
|
11/15/2006
|
Publication #:
|
|
Pub Dt:
|
03/15/2007
| | | | |
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2009
|
Application #:
|
11603121
|
Filing Dt:
|
11/22/2006
|
Publication #:
|
|
Pub Dt:
|
06/14/2007
| | | | |
Title:
|
REFERENCE VOLTAGE GENERATING CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
11605309
|
Filing Dt:
|
11/29/2006
|
Publication #:
|
|
Pub Dt:
|
06/07/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11616452
|
Filing Dt:
|
12/27/2006
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
11616755
|
Filing Dt:
|
12/27/2006
|
Publication #:
|
|
Pub Dt:
|
04/17/2008
| | | | |
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
11617379
|
Filing Dt:
|
12/28/2006
|
Publication #:
|
|
Pub Dt:
|
04/17/2008
| | | | |
Title:
|
SEMICONDUCTOR MEMORY AND MEMORY MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
|
Application #:
|
11623677
|
Filing Dt:
|
01/16/2007
|
Publication #:
|
|
Pub Dt:
|
07/26/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE HAVING PHASE CHANGE MEMORY CELLS ARRANGED IN A CHECKER MANNER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2008
|
Application #:
|
11623999
|
Filing Dt:
|
01/17/2007
|
Publication #:
|
|
Pub Dt:
|
08/02/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR PAD ALIGNED MULTIPROBE WAFER TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
11640388
|
Filing Dt:
|
12/18/2006
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
SEMICONDUCTOR STORAGE DEVICE AND REFRESH CONTROL METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2010
|
Application #:
|
11682662
|
Filing Dt:
|
03/06/2007
|
Publication #:
|
|
Pub Dt:
|
09/13/2007
| | | | |
Title:
|
DLL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11690032
|
Filing Dt:
|
03/22/2007
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
LAMINATED MEMORY HAVING AUTONOMICALLY AND SEQUENTIALLY ACTIVATING OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
11698892
|
Filing Dt:
|
01/29/2007
|
Publication #:
|
|
Pub Dt:
|
08/02/2007
| | | | |
Title:
|
TIMING ADJUSTMENT CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
11706409
|
Filing Dt:
|
02/15/2007
|
Publication #:
|
|
Pub Dt:
|
06/28/2007
| | | | |
Title:
|
SENSE AMPLIFIER FOR SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/2009
|
Application #:
|
11709191
|
Filing Dt:
|
02/22/2007
|
Publication #:
|
|
Pub Dt:
|
08/30/2007
| | | | |
Title:
|
TEMPERATURE DETECTION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
11710941
|
Filing Dt:
|
02/27/2007
|
Publication #:
|
|
Pub Dt:
|
09/06/2007
| | | | |
Title:
|
OPEN-DRAIN OUTPUT CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
11710965
|
Filing Dt:
|
02/27/2007
|
Publication #:
|
|
Pub Dt:
|
08/30/2007
| | | | |
Title:
|
METHOD FOR DESIGNING SEMICONDUCTOR PACKAGE, SYSTEM FOR AIDING TO DESIGN SEMICONDUCTOR PACKAGE, AND COMPUTER PROGRAM PRODUCT THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2008
|
Application #:
|
11712440
|
Filing Dt:
|
03/01/2007
|
Publication #:
|
|
Pub Dt:
|
06/28/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2010
|
Application #:
|
11715463
|
Filing Dt:
|
03/08/2007
|
Publication #:
|
|
Pub Dt:
|
09/13/2007
| | | | |
Title:
|
MASK DATA GENERATION METHOD AND MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2008
|
Application #:
|
11723609
|
Filing Dt:
|
03/21/2007
|
Publication #:
|
|
Pub Dt:
|
09/27/2007
| | | | |
Title:
|
WORD LINE DRIVING CIRCUIT PUTTING WORD LINE INTO ONE OF HIGH LEVEL, LOW LEVEL AND HIGH IMPEDANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2008
|
Application #:
|
11723655
|
Filing Dt:
|
03/21/2007
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
REFERENCE POTENTIAL GENERATING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
|
Application #:
|
11744694
|
Filing Dt:
|
05/04/2007
|
Publication #:
|
|
Pub Dt:
|
12/13/2007
| | | | |
Title:
|
SIGNAL DISTRIBUTION ARCHITECTURE AND SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
11747552
|
Filing Dt:
|
05/11/2007
|
Publication #:
|
|
Pub Dt:
|
09/06/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2009
|
Application #:
|
11760830
|
Filing Dt:
|
06/11/2007
|
Publication #:
|
|
Pub Dt:
|
12/27/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A TEST-VOLTAGE GENERATION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2009
|
Application #:
|
11760831
|
Filing Dt:
|
06/11/2007
|
Publication #:
|
|
Pub Dt:
|
12/27/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
11761470
|
Filing Dt:
|
06/12/2007
|
Publication #:
|
|
Pub Dt:
|
12/20/2007
| | | | |
Title:
|
STACKED SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
11768981
|
Filing Dt:
|
06/27/2007
|
Publication #:
|
|
Pub Dt:
|
10/25/2007
| | | | |
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
11771537
|
Filing Dt:
|
06/29/2007
|
Publication #:
|
|
Pub Dt:
|
05/29/2008
| | | | |
Title:
|
NONVOLATILE MEMORY DEVICE AND CONTROL METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2009
|
Application #:
|
11773152
|
Filing Dt:
|
07/03/2007
|
Publication #:
|
|
Pub Dt:
|
01/17/2008
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2009
|
Application #:
|
11781757
|
Filing Dt:
|
07/23/2007
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2009
|
Application #:
|
11790601
|
Filing Dt:
|
04/26/2007
|
Publication #:
|
|
Pub Dt:
|
11/01/2007
| | | | |
Title:
|
Waveform width adjusting circuit with selective control delay
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2010
|
Application #:
|
11800647
|
Filing Dt:
|
05/07/2007
|
Publication #:
|
|
Pub Dt:
|
11/29/2007
| | | | |
Title:
|
DESIGN METHOD AND APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11804179
|
Filing Dt:
|
05/17/2007
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE, MEMORY MODULE HAVING THE SAME, THE TEST METHOD OF MEMORY MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2010
|
Application #:
|
11806027
|
Filing Dt:
|
05/29/2007
|
Publication #:
|
|
Pub Dt:
|
12/27/2007
| | | | |
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
11806438
|
Filing Dt:
|
05/31/2007
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
SEMICONDUCTOR STORAGE DEVICE AND REFRESH CONTROL METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
11806451
|
Filing Dt:
|
05/31/2007
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11822333
|
Filing Dt:
|
07/05/2007
|
Publication #:
|
|
Pub Dt:
|
11/01/2007
| | | | |
Title:
|
REFRESH PERIOD GENERATING CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2009
|
Application #:
|
11822598
|
Filing Dt:
|
07/09/2007
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
11832727
|
Filing Dt:
|
08/02/2007
|
Publication #:
|
|
Pub Dt:
|
11/29/2007
| | | | |
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/2009
|
Application #:
|
11839668
|
Filing Dt:
|
08/16/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
INPUT AND OUTPUT CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2009
|
Application #:
|
11850748
|
Filing Dt:
|
09/06/2007
|
Publication #:
|
|
Pub Dt:
|
12/27/2007
| | | | |
Title:
|
LEVEL-CONVERSION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
11872516
|
Filing Dt:
|
10/15/2007
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND WRITE CONTROL METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2012
|
Application #:
|
11878574
|
Filing Dt:
|
07/25/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
APPARATUS INCLUDING DEFECT CORRECTING SYSTEM WHICH REPEATS A CORRECTING OF A RETICLE PATTERN DEFECT AND A CORRECTING METHOD USING THE APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2009
|
Application #:
|
11882657
|
Filing Dt:
|
08/03/2007
|
Publication #:
|
|
Pub Dt:
|
12/20/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH DELAY SECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/2009
|
Application #:
|
11882801
|
Filing Dt:
|
08/06/2007
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
LATENCY COUNTER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
11889837
|
Filing Dt:
|
08/16/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
OUTPUT CIRCUIT OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2009
|
Application #:
|
11890438
|
Filing Dt:
|
08/06/2007
|
Publication #:
|
|
Pub Dt:
|
12/27/2007
| | | | |
Title:
|
DATA TRANSMISSION SYSTEM AND DATA TRANSMISSION APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
11892229
|
Filing Dt:
|
08/21/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE COMPRISING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
|
Application #:
|
11892512
|
Filing Dt:
|
08/23/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A PSEUDO POWER SUPPLY WIRING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2009
|
Application #:
|
11892525
|
Filing Dt:
|
08/23/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
DLL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2010
|
Application #:
|
11895695
|
Filing Dt:
|
08/27/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH MINIMUM BURST LENGTH BIT TRANSFER IN PARALLEL TO AND FROM A FIFO BLOCK
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
11902006
|
Filing Dt:
|
09/18/2007
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2010
|
Application #:
|
11907208
|
Filing Dt:
|
10/10/2007
|
Publication #:
|
|
Pub Dt:
|
04/17/2008
| | | | |
Title:
|
MEMORY CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE MEMORY CIRCUIT, THE MEMORY CIRCUIT INCLUDING SELECTORS FOR SELECTING A DATA HOLDING CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
11907863
|
Filing Dt:
|
10/18/2007
|
Publication #:
|
|
Pub Dt:
|
02/28/2008
| | | | |
Title:
|
DELAY CIRCUIT AND SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2009
|
Application #:
|
11907876
|
Filing Dt:
|
10/18/2007
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
STACKED MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11924353
|
Filing Dt:
|
10/25/2007
|
Publication #:
|
|
Pub Dt:
|
04/24/2008
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE HAVING A MAIN AMPLIFIER EQUIPPED WITH A CURRENT CONTROL CIRCUIT IN A BURST READ OPERATION
|
|