Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 012845/0590 | |
| Pages: | 11 |
| | Recorded: | 04/22/2002 | | |
| Conveyance: | MERGER (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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08/04/1998
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Application #:
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08963510
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Filing Dt:
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11/03/1997
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Title:
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REALISTIC WORST-CASE CIRCUIT SIMULATION SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09246469
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Filing Dt:
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02/09/1999
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Title:
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SYSTEM, IC CHIP, ON-CHIP TEST STRUCTURE, AND CORRESPONDING METHOD FOR MODELING ONE OR MORE TARGET INTERCONNECT CAPACITANCES
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09757066
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Filing Dt:
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01/08/2001
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Publication #:
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Pub Dt:
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05/10/2001
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Title:
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SYSTEM, IC CHIP, ON-CHIP TEST STRUCTURE, AND CORRESPONDING METHOD FOR MODELING ONE OR MORE TARGET INTERCONNECT CAPACITANCES
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09757067
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Filing Dt:
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01/08/2001
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Title:
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System, IC chip, on-chip test structure, and corresponding method for modeling one or more target interconnect capacitances
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Assignee
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| 1982A ZANKER ROAD |
| SAN JOSE, CALIFORNIA 95112 |
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Correspondence name and address
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FLEHR HOHBACH TEST
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ALDO J. TEST
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FOUR EMBARCADERO CENTER
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SUITE 3400
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SAN FRANCISCO, CA 94111-4187
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