Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 017105/0594 | |
| Pages: | 9 |
| | Recorded: | 02/02/2006 | | |
Attorney Dkt #: | 6854-12 |
Conveyance: | SECURITY AGREEMENT |
|
Total properties:
10
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10118242
|
Filing Dt:
|
04/09/2002
|
Publication #:
|
|
Pub Dt:
|
10/09/2003
| | | | |
Title:
|
APPARATUS AND METHOD FOR HANDLING OF MULTI-LEVEL CIRCUIT DESIGN DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
10172996
|
Filing Dt:
|
06/18/2002
|
Publication #:
|
|
Pub Dt:
|
12/18/2003
| | | | |
Title:
|
METHOD FOR DETECTING BUS CONTENTION FROM RTL DESCRIPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2005
|
Application #:
|
10217535
|
Filing Dt:
|
08/14/2002
|
Publication #:
|
|
Pub Dt:
|
02/19/2004
| | | | |
Title:
|
METHOD FOR DETERMINING FAULT COVERAGE FROM RTL DESCRIPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10631755
|
Filing Dt:
|
08/01/2003
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
IDENTIFICATION AND IMPLEMENTATION OF CLOCK GATING IN THE DESIGN OF INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10695803
|
Filing Dt:
|
10/30/2003
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
METHOD FOR CLOCK SYNCHRONIZATION VALIDATION IN INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
10711493
|
Filing Dt:
|
09/21/2004
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
A METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR GENERATING AND VERIFYING ISOLATION LOGIC MODULES IN DESIGN OF INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2006
|
Application #:
|
10711971
|
Filing Dt:
|
10/15/2004
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
A METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR AUTOMATIC INSERTION AND CORRECTNESS VERIFICATION OF LEVEL SHIFTERS IN INTEGRATED CIRCUITS WITH MULTIPLE VOLTAGE DOMAINS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
10783091
|
Filing Dt:
|
02/23/2004
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
PATTERN RECOGNITION IN AN INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10906571
|
Filing Dt:
|
02/24/2005
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
A Method for Automatic Recognition of Handshake Data Exchange at Clock-Domain Crossing in Integrated Circuit Design
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
11260225
|
Filing Dt:
|
10/28/2005
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
CHIP DEVELOPMENT SYSTEM ENABLED FOR THE HANDLING OF MULTI-LEVEL CIRCUIT DESIGN DATA
|
|
Assignee
|
|
|
525 UNIVERSITY AVENUE |
SUITE 700 |
PALO ALTO, CALIFORNIA 94301 |
|
Correspondence name and address
|
|
JEFFREY A. O'CONNELL, ESQ.
|
|
ONE MARITIME PLAZA
|
|
18TH FLOOR
|
|
SAN FRANCISCO, CA 94111
|
Search Results as of:
09/23/2024 03:48 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|