Patent Assignment Details
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Reel/Frame: | 045736/0594 | |
| Pages: | 3 |
| | Recorded: | 05/07/2018 | | |
Attorney Dkt #: | KILOP036 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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15729638
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Filing Dt:
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10/10/2017
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Publication #:
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Pub Dt:
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04/12/2018
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Title:
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Vertical Thyristor Memory Array and Memory Array Tile Therefor
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Assignee
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2895 ZANKER ROAD |
SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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AKA CHAN LLP / GARY T. AKA
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900 LAFAYETTE STREET
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SUITE 710
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SANTA CLARA, CA 95050
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