Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 035352/0602 | |
| Pages: | 7 |
| | Recorded: | 04/07/2015 | | |
| Attorney Dkt #: | 22272-27113/US |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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09/27/2016
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Application #:
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14677206
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Filing Dt:
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04/02/2015
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Publication #:
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Pub Dt:
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10/06/2016
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Title:
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Integrated Circuit Design Optimization
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Patent #:
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Issue Dt:
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10/04/2016
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Application #:
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14678697
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Filing Dt:
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04/03/2015
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Publication #:
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Pub Dt:
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10/06/2016
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Title:
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Scaling Logic Components of Integrated Circuit Design
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Patent #:
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Issue Dt:
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09/27/2016
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Application #:
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14678702
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Filing Dt:
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04/03/2015
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Publication #:
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Pub Dt:
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10/06/2016
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Title:
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SCALING MEMORY COMPONENTS OF INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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10/04/2016
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Application #:
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14678708
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Filing Dt:
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04/03/2015
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Publication #:
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Pub Dt:
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10/06/2016
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Title:
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SCALING OF INTEGRATED CIRCUIT DESIGN INCLUDING LOGIC AND MEMORY COMPONENTS
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Patent #:
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Issue Dt:
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10/04/2016
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Application #:
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14678711
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Filing Dt:
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04/03/2015
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Publication #:
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Pub Dt:
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10/06/2016
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Title:
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INTEGRATED CIRCUIT DESIGN SCALING FOR RECOMMENDING DESIGN POINT
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Patent #:
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Issue Dt:
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10/04/2016
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Application #:
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14678715
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Filing Dt:
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04/03/2015
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Publication #:
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Pub Dt:
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10/06/2016
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Title:
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SCALING OF INTEGRATED CIRCUIT DESIGN INCLUDING HIGH-LEVEL LOGIC COMPONENTS
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Assignee
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| 2130 GOLD ST., STE. 100 |
| SAN JOSE, CALIFORNIA 95002 |
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Correspondence name and address
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GOUTHAM KONDAPALLI
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FENWICK & WEST LLP
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801 CALIFORNIA STREET
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MOUNTAIN VIEW, CA 94041
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