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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:042187/0603   Pages: 17
Recorded: 04/29/2017
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 14
1
Patent #:
Issue Dt:
11/21/2000
Application #:
09376862
Filing Dt:
08/18/1999
Title:
CONTROLLED CURRENT SOURCE FOR ACCELERATED SWITCHING
2
Patent #:
Issue Dt:
08/30/2005
Application #:
10101328
Filing Dt:
03/19/2002
Publication #:
Pub Dt:
11/28/2002
Title:
INTEGRATED CIRCUIT INCLUDING A CAPACITOR WITH A HIGH CAPACITANCE DENSITY
3
Patent #:
Issue Dt:
09/14/2004
Application #:
10262765
Filing Dt:
10/02/2002
Publication #:
Pub Dt:
04/08/2004
Title:
CAPACITOR COUPLED DYNAMIC BIAS BOOSTING CIRCUIT FOR A POWER AMPLIFIER
4
Patent #:
Issue Dt:
03/17/2009
Application #:
10525598
Filing Dt:
02/25/2005
Publication #:
Pub Dt:
07/13/2006
Title:
INTEGRATED CIRCUIT WITH EMBEDDED IDENTIFICATION CODE
5
Patent #:
Issue Dt:
05/27/2008
Application #:
10544058
Filing Dt:
07/29/2005
Publication #:
Pub Dt:
06/22/2006
Title:
BOUNDARY SCAN CIRCUIT WITH INTEGRATED SENSOR FOR SENSING PHYSICAL OPERATING PARAMETERS
6
Patent #:
Issue Dt:
06/29/2010
Application #:
10567070
Filing Dt:
02/03/2006
Publication #:
Pub Dt:
11/09/2006
Title:
ERASE AND READ SCHEMES FOR CHARGE TRAPPING NON-VOLATILE MEMORIES
7
Patent #:
Issue Dt:
11/04/2008
Application #:
11575301
Filing Dt:
03/14/2007
Publication #:
Pub Dt:
04/24/2008
Title:
BIAS CIRCUITS
8
Patent #:
Issue Dt:
09/18/2012
Application #:
11579677
Filing Dt:
11/05/2007
Publication #:
Pub Dt:
11/10/2011
Title:
METHOD OF ASSEMBLY AND ASSEMBLY THUS MADE
9
Patent #:
Issue Dt:
04/19/2016
Application #:
11628131
Filing Dt:
11/28/2006
Publication #:
Pub Dt:
01/24/2008
Title:
Chip Having Two Groups Of Chip Contacts
10
Patent #:
Issue Dt:
02/21/2012
Application #:
12161786
Filing Dt:
07/22/2008
Publication #:
Pub Dt:
03/17/2011
Title:
PROTECTED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
11
Patent #:
Issue Dt:
08/23/2011
Application #:
12479517
Filing Dt:
06/05/2009
Publication #:
Pub Dt:
12/09/2010
Title:
POWER ISLAND WITH INDEPENDENT POWER CHARACTERISTICS FOR MEMORY AND LOGIC
12
Patent #:
Issue Dt:
11/17/2015
Application #:
12665840
Filing Dt:
12/21/2009
Publication #:
Pub Dt:
07/15/2010
Title:
ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING AN ELECTRONIC DEVICE
13
Patent #:
Issue Dt:
02/24/2015
Application #:
13270898
Filing Dt:
10/11/2011
Publication #:
Pub Dt:
04/12/2012
Title:
TUNNEL FIELD EFFECT TRANSISTOR
14
Patent #:
Issue Dt:
10/07/2014
Application #:
13346031
Filing Dt:
01/09/2012
Publication #:
Pub Dt:
07/12/2012
Title:
SIGNAL PROCESSING METHOD FOR ENHANCING A DYNAMIC RANGE OF A SIGNAL
Assignor
1
Exec Dt:
04/12/2017
Assignee
1
1209 ORANGE STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
ERIC R. SCHEUERLEIN
626 JEFFERSON AVENUE, SUITE 7
SAN FRANCISCO, CA 94063

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