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1095
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Patent #:
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Issue Dt:
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01/05/2010
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Application #:
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11237095
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Filing Dt:
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09/28/2005
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Publication #:
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Pub Dt:
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03/29/2007
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Title:
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INTEGRATED CIRCUIT WITH DEPLETION MODE JFET
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Patent #:
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Issue Dt:
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11/06/2007
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Application #:
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11237410
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Filing Dt:
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09/28/2005
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Title:
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CALIBRATION STANDARD FOR TRANSMISSION ELECTRON MICROSCOPY
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Patent #:
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Issue Dt:
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07/08/2008
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Application #:
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11248509
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Filing Dt:
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10/12/2005
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Publication #:
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Pub Dt:
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06/15/2006
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Title:
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APPARATUS TO PASSIVATE INDUCTIVELY OR CAPACITIVELY COUPLED SURFACE CURRENTS UNDER CAPACITOR STRUCTURES
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Patent #:
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Issue Dt:
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09/01/2009
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Application #:
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11258253
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Filing Dt:
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10/25/2005
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Publication #:
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Pub Dt:
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02/16/2006
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Title:
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I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
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Patent #:
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Issue Dt:
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11/17/2009
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Application #:
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11262173
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Filing Dt:
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10/28/2005
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Title:
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SHALLOW TRENCH ISOLATION STRUCTURE WITH LOW TRENCH PARASITIC CAPACITANCE
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Patent #:
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Issue Dt:
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08/04/2009
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Application #:
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11265040
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Filing Dt:
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11/02/2005
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Publication #:
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Pub Dt:
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05/03/2007
| | | | |
Title:
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METHOD OF DESIGN BASED PROCESS CONTROL OPTIMIZATION
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Patent #:
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Issue Dt:
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12/22/2009
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Application #:
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11265062
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Filing Dt:
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11/02/2005
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Publication #:
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Pub Dt:
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03/16/2006
| | | | |
Title:
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INTERDIGITADED CAPACITORS
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Patent #:
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Issue Dt:
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02/05/2008
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Application #:
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11266133
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Filing Dt:
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11/02/2005
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Publication #:
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Pub Dt:
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05/03/2007
| | | | |
Title:
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MULTI-SURFACED PLATE-TO-PLATE CAPACITOR AND METHOD OF FORMING SAME
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Patent #:
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Issue Dt:
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02/19/2008
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Application #:
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11273857
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Filing Dt:
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11/15/2005
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Publication #:
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Pub Dt:
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05/17/2007
| | | | |
Title:
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EMBEDDED TEST CIRCUITRY AND A METHOD FOR TESTING A SEMICONDUCTOR DEVICE FOR BREAKDOWN, WEAROUT OR FAILURE
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Patent #:
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Issue Dt:
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10/14/2008
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Application #:
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11323398
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Filing Dt:
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12/29/2005
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Publication #:
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Pub Dt:
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11/08/2007
| | | | |
Title:
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METHOD AND APPARATUS FOR DIVERTING VOID DIFFUSION IN INTEGRATED CIRCUIT CONDUCTORS
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Patent #:
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Issue Dt:
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05/22/2007
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Application #:
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11337460
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Filing Dt:
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01/23/2006
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Publication #:
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Pub Dt:
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06/08/2006
| | | | |
Title:
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PLANARIZATION WITH REDUCED DISHING
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Patent #:
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Issue Dt:
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03/11/2008
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Application #:
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11339540
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Filing Dt:
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01/26/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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CROSS-FILL PATTERN FOR METAL FILL LEVELS, POWER SUPPLY FILTERING, AND ANALOG CIRCUIT SHIELDING
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Patent #:
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Issue Dt:
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02/26/2008
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Application #:
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11348597
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Filing Dt:
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02/07/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING IMPROVED PERFORMANCE AND RELIABILITY
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11381409
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Filing Dt:
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05/03/2006
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Publication #:
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Pub Dt:
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08/24/2006
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Title:
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Adjustable Transmission Phase Shift Mask
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Patent #:
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Issue Dt:
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12/02/2008
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Application #:
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11383171
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Filing Dt:
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05/12/2006
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Publication #:
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Pub Dt:
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08/31/2006
| | | | |
Title:
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APPARATUS FOR WAFER PATTERNING TO REDUCE EDGE EXCLUSION ZONE
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Patent #:
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Issue Dt:
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07/21/2009
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Application #:
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11383670
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Filing Dt:
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05/16/2006
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Publication #:
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Pub Dt:
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11/22/2007
| | | | |
Title:
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INTEGRATED CIRCUIT WITH A TRENCH CAPACITOR STRUCTURE AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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10/16/2007
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Application #:
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11385156
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Filing Dt:
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03/21/2006
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Publication #:
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Pub Dt:
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07/27/2006
| | | | |
Title:
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PHASE-SHIFTING MASK AND SEMICONDUCTOR DEVICE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11390015
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Filing Dt:
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03/27/2006
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Publication #:
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Pub Dt:
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07/27/2006
| | | | |
Title:
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Vertical replacement-gate junction field-effect transistor
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Patent #:
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Issue Dt:
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04/10/2007
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Application #:
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11403137
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Filing Dt:
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04/11/2006
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Publication #:
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Pub Dt:
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08/17/2006
| | | | |
Title:
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WAFER CHUCKING APPARATUS FOR SPIN PROCESSOR
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Patent #:
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Issue Dt:
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06/17/2008
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Application #:
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11403750
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Filing Dt:
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04/13/2006
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Publication #:
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Pub Dt:
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08/31/2006
| | | | |
Title:
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TEST SEMICONDUCTOR DEVICE AND METHOD FOR DETERMINING JOULE HEATING EFFECTS IN SUCH A DEVICE
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Patent #:
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Issue Dt:
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07/01/2008
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Application #:
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11418873
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Filing Dt:
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05/04/2006
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Publication #:
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Pub Dt:
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09/14/2006
| | | | |
Title:
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DUAL LAYER BARRIER FILM TECHNIQUES TO PREVENT RESIST POISONING
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Patent #:
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Issue Dt:
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06/03/2008
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Application #:
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11419252
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Filing Dt:
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05/19/2006
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Publication #:
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Pub Dt:
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05/17/2007
| | | | |
Title:
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A METHOD OF FORMING A SPIRAL INDUCTOR IN A SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
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08/21/2007
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Application #:
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11419356
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Filing Dt:
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05/19/2006
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Publication #:
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Pub Dt:
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05/17/2007
| | | | |
Title:
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A VERTICAL REPLACEMENT-GATE SILICON-ON-INSULATOR TRANSISTOR
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Patent #:
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|
Issue Dt:
|
08/21/2007
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Application #:
|
11419548
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Filing Dt:
|
05/22/2006
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Title:
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INTERCONNECT DIELECTRIC TUNING
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Patent #:
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|
Issue Dt:
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01/03/2012
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Application #:
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11425295
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Filing Dt:
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06/20/2006
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Publication #:
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Pub Dt:
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12/20/2007
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND PROCESS FOR REDUCING DAMAGING BREAKDOWN IN GATE DIELECTRICS
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|
|
Patent #:
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|
Issue Dt:
|
07/19/2011
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Application #:
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11427494
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Filing Dt:
|
06/29/2006
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Publication #:
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Pub Dt:
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01/17/2008
| | | | |
Title:
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METHOD TO IMPROVE METAL DEFECTS IN SEMICONDUCTOR DEVICE FABRICATION
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Patent #:
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|
Issue Dt:
|
10/20/2009
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Application #:
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11438493
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Filing Dt:
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05/22/2006
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Publication #:
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Pub Dt:
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01/04/2007
| | | | |
Title:
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SELECTIVE LASER ANNEALING OF SEMICONDUCTOR MATERIAL
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Patent #:
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|
Issue Dt:
|
11/11/2008
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Application #:
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11458270
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Filing Dt:
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07/18/2006
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Publication #:
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Pub Dt:
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11/09/2006
| | | | |
Title:
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METHOD FOR FORMING MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS
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Patent #:
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Issue Dt:
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11/20/2007
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Application #:
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11473627
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Filing Dt:
|
06/22/2006
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Publication #:
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Pub Dt:
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10/26/2006
| | | | |
Title:
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OPTICAL ERROR MINIMIZATION IN A SEMICONDUCTOR MANUFACTURING APPARATUS
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|
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Patent #:
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|
Issue Dt:
|
11/25/2008
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Application #:
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11506659
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Filing Dt:
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08/18/2006
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Publication #:
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Pub Dt:
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12/14/2006
| | | | |
Title:
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TECHNIQUES FOR FORMING PASSIVE DEVICES DURING SEMICONDUCTOR BACK-END PROCESSING
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Patent #:
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Issue Dt:
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06/16/2009
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Application #:
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11519614
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Filing Dt:
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09/12/2006
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Publication #:
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Pub Dt:
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01/11/2007
| | | | |
Title:
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DEFECT IDENTIFICATION SYSTEM AND METHOD FOR REPAIRING KILLER DEFECTS IN SEMICONDUCTOR DEVICES
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|
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Patent #:
|
|
Issue Dt:
|
09/02/2008
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Application #:
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11527108
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Filing Dt:
|
09/25/2006
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Publication #:
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|
Pub Dt:
|
01/18/2007
| | | | |
Title:
|
FAILURE ANALYSIS VEHICLE FOR YIELD ENHANCEMENT WITH SELF TEST AT SPEED BURNIN CAPABILITY FOR RELIABILITY TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2011
|
Application #:
|
11533785
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Filing Dt:
|
09/21/2006
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Publication #:
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Pub Dt:
|
03/27/2008
| | | | |
Title:
|
BIPOLAR DEVICE HAVING BURIED CONTACTS
|
|
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Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
11535501
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Filing Dt:
|
09/27/2006
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Publication #:
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|
Pub Dt:
|
03/27/2008
| | | | |
Title:
|
DIFFERENTIAL INDUCTOR FOR USE IN INTEGRATED CIRCUITS
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|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
11540056
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Filing Dt:
|
09/29/2006
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Publication #:
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|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
METHOD OF ELECTRICAL TESTING OF AN INTERGRATED CIRCUIT WITH AN ELECTRICAL PROBE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
11542864
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Filing Dt:
|
10/04/2006
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Publication #:
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|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
PROTRUDING SPACERS FOR SELF-ALIGNED CONTACTS
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|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
|
Application #:
|
11641507
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Filing Dt:
|
12/19/2006
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
III-V POWER FIELD EFFECT TRANSISTORS
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|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
11649015
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Filing Dt:
|
01/03/2007
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
FORMATION OF AN INTEGRATED CIRCUIT STRUCTURE WITH REDUCED DISHING IN METALLIZATION LEVELS
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|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
11649197
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Filing Dt:
|
01/03/2007
|
Publication #:
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|
Pub Dt:
|
12/20/2007
| | | | |
Title:
|
PROCESS FOR MAKING AN ON-CHIP VACUUM TUBE DEVICE
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Patent #:
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|
Issue Dt:
|
09/30/2008
|
Application #:
|
11670031
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Filing Dt:
|
02/01/2007
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Publication #:
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|
Pub Dt:
|
08/02/2007
| | | | |
Title:
|
FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)
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|
|
Patent #:
|
|
Issue Dt:
|
07/07/2009
|
Application #:
|
11673645
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Filing Dt:
|
02/12/2007
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Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
METHOD TO IMPROVE WRITER LEAKAGE IN A SIGE BIPOLAR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2010
|
Application #:
|
11673714
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Filing Dt:
|
02/12/2007
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Publication #:
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|
Pub Dt:
|
07/19/2007
| | | | |
Title:
|
SEMICONDUCTOR TEST DEVICE WITH HEATING CIRCUIT
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|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11695169
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Filing Dt:
|
04/02/2007
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Publication #:
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|
Pub Dt:
|
07/19/2007
| | | | |
Title:
|
Planarization with reduced dishing
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|
|
Patent #:
|
|
Issue Dt:
|
08/19/2008
|
Application #:
|
11733673
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Filing Dt:
|
04/10/2007
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Publication #:
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|
Pub Dt:
|
08/02/2007
| | | | |
Title:
|
MULTI-STEP PROCESS FOR FORMING A BARRIER FILM FOR USE IN COPPER LAYER FORMATION
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|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
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Application #:
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11736402
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Filing Dt:
|
04/17/2007
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Publication #:
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|
Pub Dt:
|
08/16/2007
| | | | |
Title:
|
DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
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Application #:
|
11741195
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Filing Dt:
|
04/27/2007
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Publication #:
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|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
HYBRID BUMP CAPACITOR
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|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
11748569
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Filing Dt:
|
05/15/2007
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Publication #:
|
|
Pub Dt:
|
09/13/2007
| | | | |
Title:
|
GUARD RING FOR IMPROVED MATCHING
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|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11769486
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Filing Dt:
|
06/27/2007
|
Publication #:
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|
Pub Dt:
|
10/25/2007
| | | | |
Title:
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OPTIMIZED MIRROR DESIGN FOR OPTICAL DIRECT WRITE
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|
|
Patent #:
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|
Issue Dt:
|
12/15/2009
|
Application #:
|
11809686
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Filing Dt:
|
05/31/2007
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
STRUCTURE AND FABRICATION METHOD FOR CAPACITORS INTEGRATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS
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|
|
Patent #:
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|
Issue Dt:
|
02/17/2009
|
Application #:
|
11809873
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Filing Dt:
|
06/01/2007
|
Publication #:
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|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
FABRICATION METHOD
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|
|
Patent #:
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|
Issue Dt:
|
09/21/2010
|
Application #:
|
11821396
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Filing Dt:
|
06/22/2007
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Publication #:
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|
Pub Dt:
|
11/01/2007
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH METAL SILICIDE REGIONS
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|
|
Patent #:
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|
Issue Dt:
|
12/15/2009
|
Application #:
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11827807
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Filing Dt:
|
07/13/2007
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Publication #:
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|
Pub Dt:
|
11/29/2007
| | | | |
Title:
|
REAL-TIME GATE ETCH CRITICAL DIMENSION CONTROL BY OXYGEN MONITORING
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|
|
Patent #:
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|
Issue Dt:
|
10/26/2010
|
Application #:
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11853417
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Filing Dt:
|
09/11/2007
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Publication #:
|
|
Pub Dt:
|
01/03/2008
| | | | |
Title:
|
CONTROL OF HOT CARRIER INJECTION IN A METAL-OXIDE SEMICONDUCTOR DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
11/03/2009
|
Application #:
|
11856196
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Filing Dt:
|
09/17/2007
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Publication #:
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|
Pub Dt:
|
03/13/2008
| | | | |
Title:
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APPARATUS FOR CONFINING INDUCTIVELY COUPLED SURFACE CURRENTS
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|
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Patent #:
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Issue Dt:
|
08/04/2009
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Application #:
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11872347
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Filing Dt:
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10/15/2007
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Publication #:
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Pub Dt:
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02/07/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH CONSTRICTED CURRENT PASSAGE
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|
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Patent #:
|
|
Issue Dt:
|
03/15/2011
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Application #:
|
11926469
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Filing Dt:
|
10/29/2007
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Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
SHALLOW TRENCH ISOLATION STRUCTURES AND A METHOD FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2009
|
Application #:
|
11927950
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Filing Dt:
|
10/30/2007
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
DUAL-GATE METAL-OXIDE-SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2010
|
Application #:
|
11927978
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Filing Dt:
|
10/30/2007
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Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE FORMED USING A SACRIFICIAL STRUCTURE
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|
|
Patent #:
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|
Issue Dt:
|
07/14/2009
|
Application #:
|
11937199
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Filing Dt:
|
11/08/2007
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Publication #:
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|
Pub Dt:
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03/13/2008
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Title:
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VOLTAGE CONTRAST MONITOR FOR INTEGRATED CIRCUIT DEFECTS
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Patent #:
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Issue Dt:
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03/02/2010
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Application #:
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11939482
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Filing Dt:
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11/13/2007
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Title:
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METHOD OF TREATING METAL AND METAL SALTS TO ENABLE THIN LAYER DEPOSITION IN SEMICONDUCTOR PROCESSING
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Patent #:
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Issue Dt:
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07/21/2009
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Application #:
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11964920
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12/27/2007
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Publication #:
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Pub Dt:
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07/03/2008
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Title:
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FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12021728
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Filing Dt:
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01/29/2008
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Publication #:
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Pub Dt:
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06/26/2008
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Title:
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DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING Si1-xGex AS SACRIFICIAL MATERIAL
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Patent #:
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NONE
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Application #:
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12034750
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02/21/2008
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Publication #:
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Pub Dt:
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06/12/2008
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Title:
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Substrate Laser Marking
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Patent #:
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NONE
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Application #:
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12114589
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Filing Dt:
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05/02/2008
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Publication #:
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Pub Dt:
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11/13/2008
| | | | |
Title:
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TRANSISTOR FABRICATION METHOD
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Patent #:
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04/19/2011
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12117379
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05/08/2008
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Pub Dt:
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09/04/2008
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Title:
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YIELD PROFILE MANIPULATOR
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01/12/2010
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12191171
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Filing Dt:
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08/13/2008
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Publication #:
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Pub Dt:
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12/11/2008
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Title:
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METHODS AND STRUCTURE FOR FORMING COPPER BARRIER LAYERS INTEGRAL WITH SEMICONDUCTOR SUBSTRATES STRUCTURES
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Patent #:
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Issue Dt:
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05/11/2010
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Application #:
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12243137
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10/01/2008
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Publication #:
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Pub Dt:
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01/29/2009
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Title:
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MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
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Patent #:
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Issue Dt:
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06/14/2011
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Application #:
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12253403
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Filing Dt:
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10/17/2008
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Publication #:
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Pub Dt:
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02/12/2009
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Title:
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ELECTRICAL DEVICES HAVING ADJUSTABLE CAPACITANCE
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Patent #:
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Issue Dt:
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04/20/2010
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Application #:
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12319603
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Filing Dt:
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01/09/2009
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Publication #:
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Pub Dt:
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05/21/2009
| | | | |
Title:
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METHOD OF FABRICATING A VERTICAL TRANSISTOR AND CAPACITOR
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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12339407
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Filing Dt:
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12/19/2008
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Publication #:
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Pub Dt:
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06/24/2010
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Title:
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FILL PATTERNING FOR SYMMETRICAL CIRCUITS
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Patent #:
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03/01/2011
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12476994
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06/02/2009
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Publication #:
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Pub Dt:
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09/24/2009
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Title:
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METHOD TO IMPROVE WRITER LEAKAGE IN SIGE BIPOLAR DEVICE
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Patent #:
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01/17/2012
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12502057
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Filing Dt:
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07/13/2009
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Publication #:
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Pub Dt:
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11/05/2009
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Title:
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METHOD FOR ABATING EFFLUENT FROM AN ETCHING PROCESS
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Patent #:
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Issue Dt:
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05/24/2011
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Application #:
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12506746
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Filing Dt:
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07/21/2009
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Publication #:
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Pub Dt:
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12/03/2009
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Title:
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I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
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Patent #:
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Issue Dt:
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03/27/2012
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Application #:
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12516301
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Filing Dt:
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05/26/2009
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Publication #:
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Pub Dt:
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12/16/2010
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Title:
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INTEGRATED CIRCUIT INDUCTORS WITH REDUCED MAGNETIC COUPLING
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Patent #:
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Issue Dt:
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04/12/2011
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12523368
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Filing Dt:
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07/16/2009
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Publication #:
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Pub Dt:
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03/18/2010
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Title:
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METHOD TO REDUCE COLLECTOR RESISTANCE OF A BIPOLAR TRANSISTOR AND INTEGRATION INTO A STANDARD CMOS FLOW
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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12555082
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Filing Dt:
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09/08/2009
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Publication #:
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Pub Dt:
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12/31/2009
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Title:
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METHOD OF MANUFACTURING A LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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09/20/2011
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Application #:
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12574426
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Filing Dt:
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10/06/2009
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Title:
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METHOD CHARACTERIZING MATERIALS FOR A TRENCH ISOLATION STRUCTURE HAVING LOW TRENCH PARASITIC CAPACITANCE
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Patent #:
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Issue Dt:
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06/07/2011
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Application #:
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12574479
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Filing Dt:
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10/06/2009
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Publication #:
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Pub Dt:
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01/28/2010
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Title:
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BI-AXIAL TEXTURING OF HIGH-K DIELECTRIC FILMS TO REDUCE LEAKAGE CURRENTS
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Patent #:
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Issue Dt:
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03/22/2011
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Application #:
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12610733
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Filing Dt:
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11/02/2009
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Publication #:
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Pub Dt:
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02/25/2010
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Title:
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STRUCTURE AND FABRICATION METHOD FOR CAPACITORS INTEGRATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS
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Patent #:
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Issue Dt:
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10/18/2011
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Application #:
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12616050
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Filing Dt:
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11/10/2009
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Pub Dt:
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03/11/2010
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Title:
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INTERDIGITATED CAPACITORS
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Patent #:
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02/21/2012
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12618936
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11/16/2009
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Publication #:
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Pub Dt:
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09/02/2010
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Title:
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METHOD FOR SEPARATING A SEMICONDUCTOR WAFER INTO INDIVIDUAL SEMICONDUCTOR DIES USING AN IMPLANTED IMPURITY
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Patent #:
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Issue Dt:
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10/04/2011
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12689749
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01/19/2010
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Pub Dt:
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05/13/2010
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Title:
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TRANSISTOR FABRICATION METHOD
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Patent #:
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03/22/2011
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12727304
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03/19/2010
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Pub Dt:
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07/08/2010
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Title:
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MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
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08/14/2012
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12741839
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07/08/2010
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Pub Dt:
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10/28/2010
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Title:
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CHIP IDENTIFICATION USING TOP METAL LAYER
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Issue Dt:
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10/25/2011
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12764004
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04/20/2010
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Pub Dt:
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08/12/2010
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Title:
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DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES
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02/26/2013
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12885722
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09/20/2010
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Pub Dt:
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01/13/2011
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Title:
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HYBRID BUMP CAPACITOR
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01/07/2014
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12953624
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11/24/2010
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Pub Dt:
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05/24/2012
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Title:
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MITIGATION OF DETRIMENTAL BREAKDOWN OF A HIGH DIELECTRIC CONSTANT METAL-INSULATOR-METAL CAPACITOR IN A CAPACITOR BANK
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03/27/2012
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13026528
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02/14/2011
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Pub Dt:
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06/09/2011
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Title:
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MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
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Patent #:
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10/09/2012
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13046973
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03/14/2011
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Pub Dt:
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12/08/2011
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Title:
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LOGIC-BASED EDRAM USING LOCAL INTERCONNECTS TO REDUCE IMPACT OF EXTENSION CONTACT PARASITICS
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09/18/2012
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13110581
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05/18/2011
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09/08/2011
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Title:
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I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
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02/12/2013
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13222877
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08/31/2011
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12/22/2011
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Title:
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BIPOLAR DEVICE HAVING BURIED CONTACTS
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02/19/2013
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13253554
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10/05/2011
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02/16/2012
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Title:
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MASKLESS VORTEX PHASE SHIFT OPTICAL DIRECT WRITE LITHOGRAPHY
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08/14/2012
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13311299
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12/05/2011
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03/29/2012
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Title:
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SEMICONDUCTOR DEVICE AND PROCESS FOR REDUCING DAMAGING BREAKDOWN IN GATE DIELECTRICS
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11/17/2015
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13722648
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12/20/2012
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05/02/2013
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Title:
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Maskless Vortex Phase Shift Optical Direct Write Lithography
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02/18/2014
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13775922
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02/25/2013
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07/04/2013
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Title:
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METHOD FOR HEAT DISSIPATION ON SEMICONDUCTOR DEVICE
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