Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 013826/0613 | |
| Pages: | 10 |
| | Recorded: | 03/10/2003 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
5
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09466186
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Filing Dt:
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12/17/1999
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Publication #:
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Pub Dt:
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05/30/2002
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09605737
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Filing Dt:
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06/29/2000
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Title:
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FAULT PROPAGATION PATH ESTIMATING METHOD, FAULT PROPAGATION PATH ESTIMATING APPARATUS AND RECORDING MEDIA
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09686970
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Filing Dt:
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10/12/2000
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Title:
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COMPUTER SIMULATION METHOD FOR SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09768594
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Filing Dt:
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01/25/2001
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Publication #:
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Pub Dt:
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07/26/2001
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Title:
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LAYOUT DESIGN METHOD
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09779627
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Filing Dt:
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02/09/2001
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Publication #:
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Pub Dt:
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09/27/2001
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Title:
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FLIP- CHIP SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
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Assignee
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| 1753 SHIMONUMABE, NAKAHARA-KU |
| KAWASAKI, KANAGAWA 211-8668, JAPAN |
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Correspondence name and address
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YOUNG & THOMPSON
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LAUREN TERRY
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SECOND FLOOR
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745 SOUTH 23RD STREET
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ARLINGTON, VA 22202
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