Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 011215/0622 | |
| Pages: | 3 |
| | Recorded: | 10/30/2000 | | |
| Conveyance: | CORRECTION OF ASSIGNMENT REEL9766,FRAME 0576, RECORDATION DATE 02/09/00 |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2001
|
Application #:
|
09246469
|
Filing Dt:
|
02/09/1999
|
|
Title:
|
SYSTEM, IC CHIP, ON-CHIP TEST STRUCTURE, AND CORRESPONDING METHOD FOR MODELING ONE OR MORE TARGET INTERCONNECT CAPACITANCES
|
|
|
Assignee
|
|
|
|
|
| SUITE 200 |
| 4633 OLD IRONSIDES DRIVE |
| SANTA CLARA, CALIFORNIA 95054 |
|
|
Correspondence name and address
|
| |
FLEHR HOHBACH TEST ALBRITTON &
|
| |
HERBERT LLP
|
| |
STEVEN M. FREELAND
|
| |
SUITE 3400, FOUR EMBARCADERO CENTER
|
| |
SAN FRANCISCO, CA 94111-4187
|
Search Results as of:
05/30/2024 08:51 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
