Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 032656/0623 | |
| Pages: | 8 |
| | Recorded: | 04/10/2014 | | |
| Attorney Dkt #: | TIPI 3.0-116 I |
| Conveyance: | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE INCORRECTLY CITED PATENT NUMBER 6,566,720 FROM THE CHANGE OF NAME RECORDS PREVIOUSLY RECORDED ON REEL 026423 FRAME 0286. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. |
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Total properties:
1
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09794367
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Filing Dt:
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02/27/2001
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Publication #:
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Pub Dt:
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04/11/2002
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Title:
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BASE CELL LAYOUT PERMITTING RAPID LAYOUT WITH MINIMUM CLOCK LINE CAPACITANCE ON CMOS STANDARD-CELL AND GATE-ARRAY INTEGRATED CIRCUITS
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Assignee
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| 3025 ORCHARD PARKWAY |
| SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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LDLK&M
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600 SOUTH AVENUE WEST
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WESTFIELD, NJ 07090
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