skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:051971/0624   Pages: 10
Recorded: 02/29/2020
Attorney Dkt #:22524-01000
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 42
1
Patent #:
8669792
Issue Dt:
03/11/2014
Application #:
13667290
Filing Dt:
11/02/2012
Publication #:
US20130057321
Pub Dt:
03/07/2013
Title:
Voltage Mode Driver Using Pre-emphasis and De-emphasis Signals
2
Patent #:
8643516
Issue Dt:
02/04/2014
Application #:
13669137
Filing Dt:
11/05/2012
Title:
Parallel-to-Serial Converter
3
Patent #:
9286260
Issue Dt:
03/15/2016
Application #:
13851767
Filing Dt:
03/27/2013
Publication #:
US20140298075
Pub Dt:
10/02/2014
Title:
Serial-to-Parallel Converter Using Serially-Connected Stages
4
Patent #:
9337846
Issue Dt:
05/10/2016
Application #:
13922193
Filing Dt:
06/19/2013
Publication #:
US20140317432
Pub Dt:
10/23/2014
Title:
METHODS AND SYSTEMS FOR DETERMINING WHETHER A RECEIVER IS PRESENT ON A PCI-EXPRESS BUS
5
Patent #:
8952737
Issue Dt:
02/10/2015
Application #:
14065754
Filing Dt:
10/29/2013
Publication #:
US20140312946
Pub Dt:
10/23/2014
Title:
Methods and Systems for Calibration of a Delay Locked Loop
6
Patent #:
9564905
Issue Dt:
02/07/2017
Application #:
14066583
Filing Dt:
10/29/2013
Publication #:
US20140314190
Pub Dt:
10/23/2014
Title:
Methods and Systems for Clocking a Physical Layer Interface
7
Patent #:
9467149
Issue Dt:
10/11/2016
Application #:
14170064
Filing Dt:
01/31/2014
Publication #:
US20140317434
Pub Dt:
10/23/2014
Title:
Methods and Systems for Distributing Clock and Reset Signals Across An Address Macro
8
Patent #:
9349421
Issue Dt:
05/24/2016
Application #:
14171646
Filing Dt:
02/03/2014
Publication #:
US20150221350
Pub Dt:
08/06/2015
Title:
Memory Interface
9
Patent #:
9444463
Issue Dt:
09/13/2016
Application #:
14608137
Filing Dt:
01/28/2015
Publication #:
US20160218717
Pub Dt:
07/28/2016
Title:
VOLTAGE LEVEL SHIFTER
10
Patent #:
9620179
Issue Dt:
04/11/2017
Application #:
14934021
Filing Dt:
11/05/2015
Publication #:
US20160148655
Pub Dt:
05/26/2016
Title:
SENSE AMPLIFIER AND METHODS THEREOF FOR SINGLE ENDED LINE SENSING
11
Patent #:
9564183
Issue Dt:
02/07/2017
Application #:
14934050
Filing Dt:
11/05/2015
Publication #:
US20160148688
Pub Dt:
05/26/2016
Title:
SENSE AMPLIFIER HAVING A TIMING CIRCUIT FOR A PRESEARCH AND A MAIN SEARCH
12
Patent #:
9564184
Issue Dt:
02/07/2017
Application #:
14939782
Filing Dt:
11/12/2015
Publication #:
US20160148689
Pub Dt:
05/26/2016
Title:
Sense Amplifier for Single-ended Sensing
13
Patent #:
9946620
Issue Dt:
04/17/2018
Application #:
15012707
Filing Dt:
02/01/2016
Publication #:
US20160224450
Pub Dt:
08/04/2016
Title:
Memory Built-In Self Test System
14
Patent #:
9799413
Issue Dt:
10/24/2017
Application #:
15012721
Filing Dt:
02/01/2016
Publication #:
US20160224451
Pub Dt:
08/04/2016
Title:
MULTI-DOMAIN FUSE MANAGEMENT
15
Patent #:
9865361
Issue Dt:
01/09/2018
Application #:
15140242
Filing Dt:
04/27/2016
Publication #:
US20170316837
Pub Dt:
11/02/2017
Title:
Diagnostics for a Memory Device
16
Patent #:
9948310
Issue Dt:
04/17/2018
Application #:
15145735
Filing Dt:
05/03/2016
Publication #:
US20160246325
Pub Dt:
08/25/2016
Title:
METHODS AND SYSTEMS FOR CLOCKING A PHYSICAL LAYER INTERFACE
17
Patent #:
9715907
Issue Dt:
07/25/2017
Application #:
15150334
Filing Dt:
05/09/2016
Title:
OPTIMAL DATA EYE FOR IMPROVED VREF MARGIN
18
Patent #:
9613700
Issue Dt:
04/04/2017
Application #:
15183591
Filing Dt:
06/15/2016
Title:
TCAM Field Enable Logic
19
Patent #:
9954538
Issue Dt:
04/24/2018
Application #:
15192594
Filing Dt:
06/24/2016
Publication #:
US20170373696
Pub Dt:
12/28/2017
Title:
Clock Alignment Scheme for Data Macros of DDR PHY
20
Patent #:
9564180
Issue Dt:
02/07/2017
Application #:
15192697
Filing Dt:
06/24/2016
Title:
Deep-Sleep Wake Up for a Memory Device
21
Patent #:
9716492
Issue Dt:
07/25/2017
Application #:
15241664
Filing Dt:
08/19/2016
Title:
Method and Circuit for Duty Cycle Detection
22
Patent #:
10302509
Issue Dt:
05/28/2019
Application #:
15432208
Filing Dt:
02/14/2017
Publication #:
US20180164163
Pub Dt:
06/14/2018
Title:
Temperature Sensing for Integrated Circuits
23
Patent #:
9971975
Issue Dt:
05/15/2018
Application #:
15467775
Filing Dt:
03/23/2017
Publication #:
US20170323222
Pub Dt:
11/09/2017
Title:
OPTIMAL DATA EYE FOR IMPROVED VREF MARGIN
24
Patent #:
10297310
Issue Dt:
05/21/2019
Application #:
15554000
Filing Dt:
08/27/2017
Publication #:
US20180075898
Pub Dt:
03/15/2018
Title:
A SYSTEM AND METHOD FOR MULTI-CYCLE WRITE LEVELING
25
Patent #:
10312886
Issue Dt:
06/04/2019
Application #:
15573907
Filing Dt:
11/14/2017
Publication #:
US20180351537
Pub Dt:
12/06/2018
Title:
ASYNCHRONOUS CLOCK GATING CIRCUIT
26
Patent #:
10775836
Issue Dt:
09/15/2020
Application #:
15573917
Filing Dt:
11/14/2017
Publication #:
US20190004564
Pub Dt:
01/03/2019
Title:
METHOD FOR CYCLE ACCURATE DATA TRANSFER IN A SKEWED SYNCHRONOUS CLOCK DOMAIN
27
Patent #:
10725681
Issue Dt:
07/28/2020
Application #:
15573921
Filing Dt:
11/14/2017
Publication #:
US20180357002
Pub Dt:
12/13/2018
Title:
A METHOD FOR CALIBRATING THE READ LATENCY OF A DDR DRAM MODULE
28
Patent #:
10504569
Issue Dt:
12/10/2019
Application #:
15577340
Filing Dt:
11/27/2017
Publication #:
US20190066740
Pub Dt:
02/28/2019
Title:
SYSTEM AND METHOD FOR CONTROLLING PHASE ALLIGNMENT OF CLOCK SIGNALS
29
Patent #:
10361684
Issue Dt:
07/23/2019
Application #:
15654595
Filing Dt:
07/19/2017
Publication #:
US20190028090
Pub Dt:
01/24/2019
Title:
DUTY CYCLE DETECTION
30
Patent #:
10094859
Issue Dt:
10/09/2018
Application #:
15654598
Filing Dt:
07/19/2017
Title:
VOLTAGE DETECTOR
31
Patent #:
10502769
Issue Dt:
12/10/2019
Application #:
15698289
Filing Dt:
09/07/2017
Publication #:
US20190072589
Pub Dt:
03/07/2019
Title:
Digital Voltmeter
32
Patent #:
10014866
Issue Dt:
07/03/2018
Application #:
15707205
Filing Dt:
09/18/2017
Publication #:
US20180006656
Pub Dt:
01/04/2018
Title:
Clock Alignment Scheme for Data Macros of DDR PHY
33
Patent #:
10791203
Issue Dt:
09/29/2020
Application #:
15795144
Filing Dt:
10/26/2017
Publication #:
US20190132428
Pub Dt:
05/02/2019
Title:
Multi-Protocol Receiver
34
Patent #:
10061340
Issue Dt:
08/28/2018
Application #:
15879355
Filing Dt:
01/24/2018
Title:
Bandgap Reference Voltage Generator
35
Patent #:
10498564
Issue Dt:
12/03/2019
Application #:
15895915
Filing Dt:
02/13/2018
Publication #:
US20190253284
Pub Dt:
08/15/2019
Title:
RECEIVER FOR HANDLING HIGH SPEED TRANSMISSIONS
36
Patent #:
10484218
Issue Dt:
11/19/2019
Application #:
15904139
Filing Dt:
02/23/2018
Publication #:
US20190268193
Pub Dt:
08/29/2019
Title:
PWM Demodulation
37
Patent #:
10498351
Issue Dt:
12/03/2019
Application #:
15989081
Filing Dt:
05/24/2018
Publication #:
US20190363729
Pub Dt:
11/28/2019
Title:
High-Speed DAC
38
Patent #:
10650906
Issue Dt:
05/12/2020
Application #:
16059477
Filing Dt:
08/09/2018
Publication #:
US20200051658
Pub Dt:
02/13/2020
Title:
Memory Bypass Function For A Memory
39
Patent #:
10505550
Issue Dt:
12/10/2019
Application #:
16268206
Filing Dt:
02/05/2019
Title:
Method and Apparatus of Operating Synchronizing High-Speed Clock Dividers to Correct Clock Skew
40
Patent #:
10706916
Issue Dt:
07/07/2020
Application #:
16374666
Filing Dt:
04/03/2019
Title:
Method and Apparatus for Integrated Level-Shifter and Memory Clock
41
Patent #:
10742220
Issue Dt:
08/11/2020
Application #:
16398644
Filing Dt:
04/30/2019
Title:
METHOD AND APPARATUS FOR OPERATING PROGRAMMABLE CLOCK DIVIDER USING RESET PATHS
42
Patent #:
10971218
Issue Dt:
04/06/2021
Application #:
16423554
Filing Dt:
05/28/2019
Publication #:
US20200381042
Pub Dt:
12/03/2020
Title:
Method and Apparatus for Memory Noise-Free Wake-Up Protocol from Power-Down
Assignor
1
INVECAS, INC.
Exec Dt:
02/13/2020
Assignee
1
SYNOPSYS, INC.
690 EAST MIDDLEFIELD ROAD
MOUNTAIN VIEW, CALIFORNIA 94043
Correspondence name and address
RAJIV P. PATEL
801 CALIFORNIA STREET
MOUNTAIN VIEW, CA 94041

Search Results as of: 06/19/2024 07:08 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT