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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:051070/0625   Pages: 53
Recorded: 11/20/2019
Attorney Dkt #:5059-500029
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 683
Page 1 of 7
Pages: 1 2 3 4 5 6 7
1
Patent #:
Issue Dt:
04/28/1998
Application #:
08536901
Filing Dt:
09/29/1995
Title:
METHOD AND SYSTEM FOR PROGRAMMING A GATE ARRAY USING A COMPRESSED CONFIGURATION BIT STREAM
2
Patent #:
Issue Dt:
03/31/1998
Application #:
08570850
Filing Dt:
12/12/1995
Title:
METHOD AND SYSTEM FOR LAYOUT AND SCHEMATIC GENERATION FOR HETEROGENEOUS ARRAYS
3
Patent #:
Issue Dt:
06/22/1999
Application #:
08575312
Filing Dt:
12/20/1995
Title:
FIELD PROGRAMMABLE MEMORY ARRAY
4
Patent #:
Issue Dt:
06/16/1998
Application #:
08705871
Filing Dt:
08/28/1996
Title:
PERFORMANCE MONITORING THROUGH JTAG 1149.1 INTERFACE
5
Patent #:
Issue Dt:
11/03/1998
Application #:
08772706
Filing Dt:
12/23/1996
Title:
SELF REGULATING TEMPERATURE/PERFORMANCE/VOLTAGE SCHEME FOR MICROS (X86)
6
Patent #:
Issue Dt:
05/26/1998
Application #:
08803056
Filing Dt:
02/19/1997
Title:
GAIN MEMORY CELL WITH DIODE
7
Patent #:
Issue Dt:
05/30/2000
Application #:
08833367
Filing Dt:
04/04/1997
Title:
RECONFIGURABLE I/O DRAM
8
Patent #:
Issue Dt:
09/12/2000
Application #:
08853963
Filing Dt:
05/09/1997
Title:
SELF BIASED DIFFERENTIAL AMPLIFIER WITH HYSTERESIS
9
Patent #:
Issue Dt:
09/07/1999
Application #:
08873830
Filing Dt:
06/12/1997
Title:
BIDIRECTIONAL OFF-CHIP DRIVER WITH RECEIVER BYPASS
10
Patent #:
Issue Dt:
06/13/2000
Application #:
08936032
Filing Dt:
09/23/1997
Title:
METHOD OF FORMING A FLIP CHIP ASSEMBLY AND A FLIP CHIP ASSEMBLY FORMED BY THE METHOD
11
Patent #:
Issue Dt:
08/31/1999
Application #:
08942515
Filing Dt:
10/02/1997
Title:
SEMICONDUCTOR STACK STRUCTURES AND FABRICATION/SPARING METHODS UTILIZING PROGRAMMABLE SPARE CIRCUIT
12
Patent #:
Issue Dt:
04/27/1999
Application #:
08947762
Filing Dt:
10/09/1997
Title:
N INPUT PORT SWITCHING PROTOCOL FOR A RANDOM ACCESS MEMORY
13
Patent #:
Issue Dt:
12/04/2001
Application #:
09018698
Filing Dt:
02/04/1998
Title:
ELECTRONIC PACKAGE WITH INTERCONNECTED CHIPS
14
Patent #:
Issue Dt:
08/01/2000
Application #:
09055002
Filing Dt:
04/03/1998
Title:
PULL THROUGH FIFO MEMORY DEVICE
15
Patent #:
Issue Dt:
08/31/1999
Application #:
09056903
Filing Dt:
04/07/1998
Title:
DRAM CELL WITH GROOVED TRANSFER DEVICE
16
Patent #:
Issue Dt:
05/16/2000
Application #:
09079572
Filing Dt:
05/15/1998
Title:
HIGH BANDWIDTH NARROW I/O MEMORY DEVICE WITH COMMAND STACKING
17
Patent #:
Issue Dt:
09/12/2000
Application #:
09081639
Filing Dt:
05/20/1998
Title:
SELF-INITIATED SELF-REFRESH MODE FOR MEMORY MODULES
18
Patent #:
Issue Dt:
05/02/2000
Application #:
09092412
Filing Dt:
06/05/1998
Title:
PROGRAMMABLE, SELF-RESETTING DIVIDER
19
Patent #:
Issue Dt:
07/27/2004
Application #:
09105739
Filing Dt:
06/26/1998
Title:
METHOD FOR INTERCONNECTION BETWEEN TRANSFER DEVICES AND STORAGE CAPACITORS IN MEMORY CELLS AND DEVICE FORMED THEREBY
20
Patent #:
Issue Dt:
01/04/2000
Application #:
09120211
Filing Dt:
07/21/1998
Title:
LOW POWERING APPARATUS FOR AUTOMATIC REDUCTION OF POWER IN ACTIVE AND STANDBY MODES
21
Patent #:
Issue Dt:
01/23/2001
Application #:
09121933
Filing Dt:
07/24/1998
Title:
HIGH BANDWIDTH DRAM WITH LOW OPERATING POWER MODES
22
Patent #:
Issue Dt:
08/01/2000
Application #:
09159861
Filing Dt:
09/24/1998
Title:
DEVICE AND METHOD TO REDUCE POWER CONSUMPTION IN INTEGRATED SEMICONDUCTOR DEVICES USING A LOW POWER GROGGY MODE
23
Patent #:
Issue Dt:
08/01/2000
Application #:
09159898
Filing Dt:
09/24/1998
Title:
ASIC LOW POWER ACTIVITY DETECTOR TO CHANGE THRESHOLD VOLTAGE
24
Patent #:
Issue Dt:
09/12/2000
Application #:
09183342
Filing Dt:
10/30/1998
Title:
SELF REGULATING TEMPERATURE/PERFORMANCE/VOLTAGE SCHEME FOR MICROS (X86)
25
Patent #:
Issue Dt:
03/14/2000
Application #:
09189391
Filing Dt:
11/10/1998
Title:
MEMORY CELLS FOR FIELD PROGRAMMABLE MEMORY ARRAY
26
Patent #:
Issue Dt:
09/12/2000
Application #:
09189750
Filing Dt:
11/10/1998
Title:
METHOD OF OPERATING A FIELD PROGRAMMABLE MEMORY ARRAY WITH A FIELD PROGRAMMABLE GATE ARRAY
27
Patent #:
Issue Dt:
06/13/2000
Application #:
09190628
Filing Dt:
11/12/1998
Title:
FIELD PROGRAMMABLE MEMORY ARRAY
28
Patent #:
Issue Dt:
10/10/2000
Application #:
09190871
Filing Dt:
11/12/1998
Title:
PROGRAMMABLE ADDRESS DECODER FOR FIELD PROGRAMMABLE MEMORY ARRAY
29
Patent #:
Issue Dt:
03/28/2000
Application #:
09190919
Filing Dt:
11/12/1998
Title:
PROGRAMMABLE BIT LINE DRIVE MODES FOR MEMORY ARRAYS
30
Patent #:
Issue Dt:
12/05/2000
Application #:
09224766
Filing Dt:
01/04/1999
Title:
ESD PROTECTION CIRCUIT FOR MULTIPLE POWER SUUPLY ENVIRONMENTS
31
Patent #:
Issue Dt:
10/03/2000
Application #:
09239487
Filing Dt:
01/28/1999
Title:
DELAY-LOCKED-LOOP (DLL) HAVING SYMMETRICAL RISING AND FALLING CLOCK EDGE TYPE DELAYS
32
Patent #:
Issue Dt:
01/23/2001
Application #:
09283960
Filing Dt:
04/01/1999
Title:
COMPENSATED-CURRENT MIRROR OFF-CHIP DRIVER
33
Patent #:
Issue Dt:
02/06/2001
Application #:
09296807
Filing Dt:
04/23/1999
Title:
TRENCH STORAGE DYNAMIC RANDOM ACCESS MEMORY CELL WITH VERTICAL TRANSFER DEVICE
34
Patent #:
Issue Dt:
10/31/2000
Application #:
09302902
Filing Dt:
04/30/1999
Title:
IMPEDANCE CONTROL USING FUSES
35
Patent #:
Issue Dt:
04/22/2003
Application #:
09422367
Filing Dt:
10/21/1999
Title:
METHOD AND APPARATUS FOR PROCESS INDEPENDENT CLOCK SIGNAL DISTRIBUTION
36
Patent #:
Issue Dt:
04/17/2001
Application #:
09458877
Filing Dt:
12/10/1999
Title:
CONDUCTIVE LINE FEATURES FOR ENHANCED RELIABILITY OF MULTI-LAYER CERAMIC SUBSTRATES
37
Patent #:
Issue Dt:
05/08/2001
Application #:
09501393
Filing Dt:
02/09/2000
Title:
Write through function for a memory
38
Patent #:
Issue Dt:
08/28/2001
Application #:
09524661
Filing Dt:
03/13/2000
Title:
Multi-ported memory with asynchronous and synchronous protocol
39
Patent #:
Issue Dt:
04/01/2003
Application #:
09526198
Filing Dt:
03/15/2000
Title:
MACRO DESIGN TECHNIQUES TO ACCOMMODATE CHIP LEVEL WIRING AND CIRCUIT PLACEMENT ACROSS THE MACRO
40
Patent #:
Issue Dt:
12/07/2004
Application #:
09574186
Filing Dt:
05/18/2000
Title:
METHOD AND APPARATUS FOR PRESERVING THE CONTENTS OF SYNCHRONOUS DRAM THROUGH SYSTEM RESET
41
Patent #:
Issue Dt:
12/17/2002
Application #:
09588202
Filing Dt:
06/06/2000
Title:
AUTOMATIC OFF-CHIP DRIVER ADJUSTMENT BASED ON LOAD CHARACTERISTICS
42
Patent #:
Issue Dt:
06/05/2001
Application #:
09589922
Filing Dt:
06/07/2000
Title:
Impedance control using fuses
43
Patent #:
Issue Dt:
11/04/2003
Application #:
09615767
Filing Dt:
07/13/2000
Title:
UNIVERSAL BOOT CODE FOR A COMPUTER NETWORK
44
Patent #:
Issue Dt:
07/06/2004
Application #:
09617558
Filing Dt:
07/17/2000
Title:
PROGRAMMABLE COMPENSATED DELAY FOR DDR SDRAM INTERFACE USING PROGRAMMABLE DELAY LOOP FOR REFERENCE CALIBRATION
45
Patent #:
Issue Dt:
12/02/2003
Application #:
09669117
Filing Dt:
09/25/2000
Title:
COMPILABLE ADDRESS MAGNITUDE COMPARATOR FOR MEMORY ARRAY SELF-TESTING
46
Patent #:
Issue Dt:
08/06/2002
Application #:
09682638
Filing Dt:
10/01/2001
Title:
EMBEDDED CAM TEST STRUCTURE FOR FULLY TESTING ALL MATCHLINES
47
Patent #:
Issue Dt:
09/16/2003
Application #:
09683808
Filing Dt:
02/19/2002
Publication #:
Pub Dt:
08/21/2003
Title:
REDUNDANT ANTIFUSE SEGMENTS FOR IMPROVED PROGRAMMING EFFICIENCY
48
Patent #:
Issue Dt:
04/29/2003
Application #:
09690674
Filing Dt:
10/17/2000
Title:
SOI HYBRID STRUCTURE WITH SELECTIVE EPITAXIAL GROWTH OF SILICON
49
Patent #:
Issue Dt:
06/10/2003
Application #:
09731147
Filing Dt:
12/05/2000
Publication #:
Pub Dt:
08/01/2002
Title:
METHOD AND APPARATUS FOR INITIALIZING AN INTEGRATED CIRCUIT USING COMPRESSED DATA FROM A REMOTE FUSEBOX
50
Patent #:
Issue Dt:
12/17/2002
Application #:
09733295
Filing Dt:
12/08/2000
Publication #:
Pub Dt:
08/15/2002
Title:
METHOD AND APPARATUS FOR TESTING A WRITE FUNCTION OF A DUAL-PORT STATIC MEMORY CELL
51
Patent #:
Issue Dt:
02/18/2003
Application #:
09737012
Filing Dt:
12/14/2000
Publication #:
Pub Dt:
08/15/2002
Title:
METHOD FOR SUPPLY VOLTAGE DROP ANALYSIS DURING PLACEMENT PHASE OF CHIP DESIGN
52
Patent #:
Issue Dt:
10/15/2002
Application #:
09757107
Filing Dt:
01/08/2001
Publication #:
Pub Dt:
07/11/2002
Title:
LINEAR VOLTAGE CONTROLLED OSCILLATOR TRANSCONDUCTOR WITH GAIN COMPENSATION
53
Patent #:
Issue Dt:
07/16/2002
Application #:
09757267
Filing Dt:
01/09/2001
Publication #:
Pub Dt:
07/11/2002
Title:
PROGRAMMABLE LATCH DEVICE WITH INTEGRATED PROGRAMMABLE ELEMENT
54
Patent #:
Issue Dt:
04/16/2002
Application #:
09765035
Filing Dt:
01/17/2001
Title:
INTEGRATED FUSE LATCH AND SHIFT REGISTER FOR EFFICIENT PROGRAMMING AND FUSE READOUT
55
Patent #:
Issue Dt:
03/16/2004
Application #:
09768122
Filing Dt:
01/23/2001
Publication #:
Pub Dt:
07/25/2002
Title:
METHOD FOR GUARANTEEING A MINIMUM DATA STROBE VALID WINDOW AND A MINIMUM DATA VALID WINDOW FOR DDR MEMORY DEVICES
56
Patent #:
Issue Dt:
06/22/2004
Application #:
09791003
Filing Dt:
02/22/2001
Publication #:
Pub Dt:
08/22/2002
Title:
SYSTEM AND METHOD TO PREDETERMINE A BITMAP OF A SELF-TESTED EMBEDDED ARRAY
57
Patent #:
Issue Dt:
03/11/2003
Application #:
09795610
Filing Dt:
02/27/2001
Publication #:
Pub Dt:
08/29/2002
Title:
INTRINSIC DUAL GATE OXIDE MOSFET USING A DAMASCENE GATE PROCESS
58
Patent #:
Issue Dt:
08/08/2006
Application #:
09805027
Filing Dt:
03/12/2001
Publication #:
Pub Dt:
09/12/2002
Title:
COPPER TO ALUMINUM INTERLAYER INTERCONNECT USING STUD AND VIA LINER
59
Patent #:
Issue Dt:
08/13/2002
Application #:
09805420
Filing Dt:
03/13/2001
Title:
CLOCKED MEMORY DEVICE THAT INCLUDES A PROGRAMMING MECHANISM FOR SETTING WRITE RECOVERY TIME AS A FUNCTION OF THE INPUT CLOCK
60
Patent #:
Issue Dt:
12/03/2002
Application #:
09810133
Filing Dt:
03/16/2001
Publication #:
Pub Dt:
09/19/2002
Title:
CROSSTALK SUPPRESSION IN DIFFERENTIAL AC COUPLED MULTICHANNEL IC AMPLIFIERS
61
Patent #:
Issue Dt:
10/22/2002
Application #:
09810763
Filing Dt:
03/16/2001
Publication #:
Pub Dt:
09/19/2002
Title:
SUBSTITUTION OF NON-MINIMUM GROUNDRULE CELLS FOR NON-CRITICAL MINIMUM GROUNDRULE CELLS TO INCREASE YIELD
62
Patent #:
Issue Dt:
06/15/2004
Application #:
09827073
Filing Dt:
04/05/2001
Publication #:
Pub Dt:
11/21/2002
Title:
ULTRA HIGH-SPEED DDP-SRAM CACHE
63
Patent #:
Issue Dt:
12/14/2004
Application #:
09862427
Filing Dt:
05/21/2001
Publication #:
Pub Dt:
11/21/2002
Title:
SYSTEM AND METHOD FOR ANALYZING POWER DISTRIBUTION USING STATIC TIMING ANALYSIS
64
Patent #:
Issue Dt:
08/20/2002
Application #:
09870559
Filing Dt:
05/31/2001
Title:
STABILIZED DIRECT SENSING MEMORY ARCHITECTURE
65
Patent #:
Issue Dt:
08/23/2005
Application #:
09870623
Filing Dt:
05/31/2001
Publication #:
Pub Dt:
12/05/2002
Title:
METHOD AND APPARATUS FOR INTERFACE SIGNALING USING SINGLE-ENDED AND DIFFERENTIAL DATA SIGNALS
66
Patent #:
Issue Dt:
04/22/2003
Application #:
09870755
Filing Dt:
05/31/2001
Publication #:
Pub Dt:
12/05/2002
Title:
SINGLE BITLINE DIRECT SENSING ARCHITECTURE FOR HIGH SPEED MEMORY DEVICE
67
Patent #:
Issue Dt:
06/27/2006
Application #:
09885853
Filing Dt:
06/20/2001
Publication #:
Pub Dt:
12/26/2002
Title:
EXTENSION OF FATIGUE LIFE FOR C4 SOLDER BALL TO CHIP CONNECTION
68
Patent #:
Issue Dt:
08/31/2004
Application #:
09887792
Filing Dt:
06/22/2001
Publication #:
Pub Dt:
12/26/2002
Title:
PROCESS INDEPENDENT SOURCE SYNCHRONOUS DATA CAPTURE APPARATUS AND METHOD
69
Patent #:
Issue Dt:
04/22/2003
Application #:
09892396
Filing Dt:
06/27/2001
Publication #:
Pub Dt:
01/02/2003
Title:
SAVING CONTENT ADDRESSABLE MEMORY POWER THROUGH CONDITIONAL COMPARISONS
70
Patent #:
Issue Dt:
12/21/2004
Application #:
09907387
Filing Dt:
07/17/2001
Publication #:
Pub Dt:
01/23/2003
Title:
INTEGRATED REAL-TIME DATA TRACING WITH LOW PIN COUNT OUTPUT
71
Patent #:
Issue Dt:
02/11/2003
Application #:
09917059
Filing Dt:
07/27/2001
Publication #:
Pub Dt:
01/30/2003
Title:
SENSE AMPLIFIER THRESHOLD COMPENSATION
72
Patent #:
Issue Dt:
11/08/2005
Application #:
09918809
Filing Dt:
07/31/2001
Publication #:
Pub Dt:
02/06/2003
Title:
ADAPTIVE PHASE LOCKED LOOP
73
Patent #:
Issue Dt:
03/04/2003
Application #:
09974986
Filing Dt:
10/11/2001
Title:
INTERLEAVED FEEDFORWARD VCO AND PLL
74
Patent #:
Issue Dt:
03/25/2003
Application #:
09977423
Filing Dt:
10/15/2001
Publication #:
Pub Dt:
04/17/2003
Title:
METHOD AND RING OSCILLATOR FOR EVALUATING DYNAMIC CIRCUITS
75
Patent #:
Issue Dt:
01/31/2006
Application #:
09996053
Filing Dt:
11/28/2001
Publication #:
Pub Dt:
09/26/2002
Title:
ANALOG UNIDIRECTIONAL SERIAL LINK ARCHITECTURE
76
Patent #:
Issue Dt:
11/18/2003
Application #:
10059863
Filing Dt:
01/30/2002
Publication #:
Pub Dt:
07/31/2003
Title:
HIGH RELIABILITY CONTENT-ADDRESSABLE MEMORY USING SHADOW CONTENT-ADDRESSABLE MEMORY
77
Patent #:
Issue Dt:
08/17/2004
Application #:
10063212
Filing Dt:
03/29/2002
Publication #:
Pub Dt:
10/02/2003
Title:
COMPLEMENTARY TWO TRANSISTOR ROM CELL
78
Patent #:
Issue Dt:
01/24/2006
Application #:
10063394
Filing Dt:
04/18/2002
Publication #:
Pub Dt:
10/23/2003
Title:
ON CHIP TIMING ADJUSTMENT IN MULTI-CHANNEL FAST DATA TRANSFER
79
Patent #:
Issue Dt:
11/23/2004
Application #:
10063427
Filing Dt:
04/23/2002
Publication #:
Pub Dt:
10/23/2003
Title:
PHYSICAL DESIGN CHARACTERIZATION SYSTEM
80
Patent #:
Issue Dt:
12/11/2007
Application #:
10063495
Filing Dt:
04/30/2002
Publication #:
Pub Dt:
10/30/2003
Title:
TESTING OF ECC MEMORIES
81
Patent #:
Issue Dt:
12/12/2006
Application #:
10063497
Filing Dt:
04/30/2002
Publication #:
Pub Dt:
10/30/2003
Title:
OPTIMIZED ECC/REDUNDANCY FAULT RECOVERY
82
Patent #:
Issue Dt:
05/04/2004
Application #:
10063504
Filing Dt:
05/01/2002
Publication #:
Pub Dt:
11/06/2003
Title:
GLOBAL VOLTAGE BUFFER FOR VOLTAGE ISLANDS
83
Patent #:
Issue Dt:
03/28/2006
Application #:
10063859
Filing Dt:
05/20/2002
Publication #:
Pub Dt:
11/20/2003
Title:
METHOD AND APPARATUS FOR PROVIDING NOISE SUPPRESSION IN AN INTEGRATED CIRCUIT
84
Patent #:
Issue Dt:
09/21/2004
Application #:
10064921
Filing Dt:
08/29/2002
Publication #:
Pub Dt:
03/04/2004
Title:
APPARATUS FOR REDUCING SOFT ERRORS IN DYNAMIC CIRCUITS
85
Patent #:
Issue Dt:
08/16/2005
Application #:
10065475
Filing Dt:
10/22/2002
Publication #:
Pub Dt:
04/22/2004
Title:
TERMINATING RESISTOR DRIVER FOR HIGH SPEED DATA COMMUNICATION
86
Patent #:
Issue Dt:
06/13/2006
Application #:
10072346
Filing Dt:
02/06/2002
Publication #:
Pub Dt:
08/08/2002
Title:
ADDRESS WRAP FUNCTION FOR ADDRESSABLE MEMORY DEVICES
87
Patent #:
Issue Dt:
11/18/2003
Application #:
10078174
Filing Dt:
02/15/2002
Publication #:
Pub Dt:
08/21/2003
Title:
UNIQUE FEATURE DESIGN ENABLING STRUCTURAL INTEGRITY FOR ADVANCED LOW K SEMICONDUCTOR CHIPS
88
Patent #:
Issue Dt:
03/02/2004
Application #:
10116813
Filing Dt:
04/05/2002
Publication #:
Pub Dt:
08/22/2002
Title:
METHOD AND APPARATUS FOR PROCESS INDEPENDENT CLOCK SIGNAL DISTRIBUTION
89
Patent #:
Issue Dt:
12/02/2003
Application #:
10140549
Filing Dt:
05/07/2002
Publication #:
Pub Dt:
11/13/2003
Title:
SPLIT LOCAL AND CONTINUOUS BITLINE FOR FAST DOMINO READ SRAM
90
Patent #:
Issue Dt:
06/21/2005
Application #:
10176233
Filing Dt:
06/20/2002
Publication #:
Pub Dt:
12/25/2003
Title:
METHOD AND APPARATUS TO MAKE A SEMICONDUCTOR CHIP SUSCEPTIBLE TO RADIATION FAILURE
91
Patent #:
Issue Dt:
07/19/2005
Application #:
10199788
Filing Dt:
07/19/2002
Publication #:
Pub Dt:
01/22/2004
Title:
METHOD AND APPARATUS OF LOCAL WORD-LINE REDUNDANCY IN CAM
92
Patent #:
Issue Dt:
11/23/2004
Application #:
10235435
Filing Dt:
09/04/2002
Publication #:
Pub Dt:
03/04/2004
Title:
REDUNDANT CONFIGURABLE VCSEL LASER ARRAY OPTICAL LIGHT SOURCE
93
Patent #:
Issue Dt:
01/10/2006
Application #:
10248302
Filing Dt:
01/07/2003
Publication #:
Pub Dt:
07/08/2004
Title:
SIGNAL BALANCING BETWEEN VOLTAGE DOMAINS
94
Patent #:
Issue Dt:
11/30/2004
Application #:
10249273
Filing Dt:
03/27/2003
Publication #:
Pub Dt:
09/30/2004
Title:
SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY DEVICE HAVING MEMORY COMMAND CANCEL FUNCTION
95
Patent #:
Issue Dt:
05/04/2004
Application #:
10249311
Filing Dt:
03/31/2003
Title:
TRI-STATE DELAY BOOST
96
Patent #:
Issue Dt:
01/20/2009
Application #:
10249331
Filing Dt:
04/01/2003
Publication #:
Pub Dt:
10/07/2004
Title:
METHOD FOR PERFORMING A COMMAND CANCEL FUNCTION IN A DRAM
97
Patent #:
Issue Dt:
06/08/2004
Application #:
10249347
Filing Dt:
04/02/2003
Title:
GAIN CELL STRUCTURE WITH DEEP TRENCH CAPACITOR
98
Patent #:
Issue Dt:
05/10/2005
Application #:
10249545
Filing Dt:
04/17/2003
Publication #:
Pub Dt:
10/21/2004
Title:
REFERENCE CURRENT GENERATION SYSTEM AND METHOD
99
Patent #:
Issue Dt:
11/30/2004
Application #:
10249684
Filing Dt:
04/30/2003
Publication #:
Pub Dt:
11/04/2004
Title:
POWER REDUCTION BY STAGE IN INTEGRATED CIRCUIT
100
Patent #:
Issue Dt:
01/20/2004
Application #:
10249795
Filing Dt:
05/08/2003
Title:
HIGH SPEED FIR TRANSMITTER
Assignor
1
Exec Dt:
11/05/2019
Assignee
1
CANON'S COURT, VICTORIA STREET
HAMILTON, BERMUDA HM 12
Correspondence name and address
HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 828
BLOOMFIELD HILLS, MI 48303

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