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Patent #:
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Issue Dt:
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04/28/1998
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Application #:
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08536901
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Filing Dt:
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09/29/1995
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Title:
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METHOD AND SYSTEM FOR PROGRAMMING A GATE ARRAY USING A COMPRESSED CONFIGURATION BIT STREAM
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Patent #:
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Issue Dt:
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03/31/1998
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Application #:
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08570850
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Filing Dt:
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12/12/1995
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Title:
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METHOD AND SYSTEM FOR LAYOUT AND SCHEMATIC GENERATION FOR HETEROGENEOUS ARRAYS
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Patent #:
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Issue Dt:
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06/22/1999
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Application #:
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08575312
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Filing Dt:
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12/20/1995
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Title:
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FIELD PROGRAMMABLE MEMORY ARRAY
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Patent #:
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Issue Dt:
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06/16/1998
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Application #:
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08705871
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Filing Dt:
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08/28/1996
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Title:
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PERFORMANCE MONITORING THROUGH JTAG 1149.1 INTERFACE
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Patent #:
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Issue Dt:
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11/03/1998
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Application #:
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08772706
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Filing Dt:
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12/23/1996
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Title:
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SELF REGULATING TEMPERATURE/PERFORMANCE/VOLTAGE SCHEME FOR MICROS (X86)
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Patent #:
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Issue Dt:
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05/26/1998
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Application #:
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08803056
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Filing Dt:
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02/19/1997
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Title:
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GAIN MEMORY CELL WITH DIODE
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Patent #:
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Issue Dt:
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05/30/2000
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Application #:
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08833367
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Filing Dt:
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04/04/1997
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Title:
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RECONFIGURABLE I/O DRAM
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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08853963
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Filing Dt:
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05/09/1997
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Title:
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SELF BIASED DIFFERENTIAL AMPLIFIER WITH HYSTERESIS
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Patent #:
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Issue Dt:
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09/07/1999
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Application #:
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08873830
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Filing Dt:
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06/12/1997
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Title:
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BIDIRECTIONAL OFF-CHIP DRIVER WITH RECEIVER BYPASS
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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08936032
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Filing Dt:
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09/23/1997
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Title:
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METHOD OF FORMING A FLIP CHIP ASSEMBLY AND A FLIP CHIP ASSEMBLY FORMED BY THE METHOD
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Patent #:
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Issue Dt:
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08/31/1999
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Application #:
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08942515
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Filing Dt:
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10/02/1997
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Title:
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SEMICONDUCTOR STACK STRUCTURES AND FABRICATION/SPARING METHODS UTILIZING PROGRAMMABLE SPARE CIRCUIT
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Patent #:
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Issue Dt:
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04/27/1999
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Application #:
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08947762
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Filing Dt:
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10/09/1997
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Title:
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N INPUT PORT SWITCHING PROTOCOL FOR A RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09018698
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Filing Dt:
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02/04/1998
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Title:
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ELECTRONIC PACKAGE WITH INTERCONNECTED CHIPS
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09055002
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Filing Dt:
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04/03/1998
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Title:
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PULL THROUGH FIFO MEMORY DEVICE
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Patent #:
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Issue Dt:
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08/31/1999
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Application #:
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09056903
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Filing Dt:
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04/07/1998
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Title:
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DRAM CELL WITH GROOVED TRANSFER DEVICE
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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09079572
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Filing Dt:
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05/15/1998
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Title:
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HIGH BANDWIDTH NARROW I/O MEMORY DEVICE WITH COMMAND STACKING
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09081639
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Filing Dt:
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05/20/1998
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Title:
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SELF-INITIATED SELF-REFRESH MODE FOR MEMORY MODULES
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Patent #:
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Issue Dt:
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05/02/2000
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Application #:
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09092412
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Filing Dt:
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06/05/1998
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Title:
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PROGRAMMABLE, SELF-RESETTING DIVIDER
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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09105739
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Filing Dt:
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06/26/1998
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Title:
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METHOD FOR INTERCONNECTION BETWEEN TRANSFER DEVICES AND STORAGE CAPACITORS IN MEMORY CELLS AND DEVICE FORMED THEREBY
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Patent #:
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Issue Dt:
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01/04/2000
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Application #:
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09120211
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Filing Dt:
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07/21/1998
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Title:
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LOW POWERING APPARATUS FOR AUTOMATIC REDUCTION OF POWER IN ACTIVE AND STANDBY MODES
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09121933
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Filing Dt:
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07/24/1998
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Title:
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HIGH BANDWIDTH DRAM WITH LOW OPERATING POWER MODES
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09159861
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Filing Dt:
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09/24/1998
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Title:
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DEVICE AND METHOD TO REDUCE POWER CONSUMPTION IN INTEGRATED SEMICONDUCTOR DEVICES USING A LOW POWER GROGGY MODE
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09159898
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Filing Dt:
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09/24/1998
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Title:
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ASIC LOW POWER ACTIVITY DETECTOR TO CHANGE THRESHOLD VOLTAGE
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09183342
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Filing Dt:
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10/30/1998
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Title:
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SELF REGULATING TEMPERATURE/PERFORMANCE/VOLTAGE SCHEME FOR MICROS (X86)
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Patent #:
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Issue Dt:
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03/14/2000
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Application #:
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09189391
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Filing Dt:
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11/10/1998
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Title:
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MEMORY CELLS FOR FIELD PROGRAMMABLE MEMORY ARRAY
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09189750
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Filing Dt:
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11/10/1998
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Title:
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METHOD OF OPERATING A FIELD PROGRAMMABLE MEMORY ARRAY WITH A FIELD PROGRAMMABLE GATE ARRAY
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09190628
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Filing Dt:
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11/12/1998
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Title:
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FIELD PROGRAMMABLE MEMORY ARRAY
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Patent #:
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Issue Dt:
|
10/10/2000
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Application #:
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09190871
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Filing Dt:
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11/12/1998
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Title:
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PROGRAMMABLE ADDRESS DECODER FOR FIELD PROGRAMMABLE MEMORY ARRAY
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09190919
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Filing Dt:
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11/12/1998
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Title:
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PROGRAMMABLE BIT LINE DRIVE MODES FOR MEMORY ARRAYS
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09224766
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Filing Dt:
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01/04/1999
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Title:
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ESD PROTECTION CIRCUIT FOR MULTIPLE POWER SUUPLY ENVIRONMENTS
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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09239487
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Filing Dt:
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01/28/1999
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Title:
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DELAY-LOCKED-LOOP (DLL) HAVING SYMMETRICAL RISING AND FALLING CLOCK EDGE TYPE DELAYS
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09283960
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Filing Dt:
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04/01/1999
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Title:
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COMPENSATED-CURRENT MIRROR OFF-CHIP DRIVER
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Patent #:
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Issue Dt:
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02/06/2001
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Application #:
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09296807
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Filing Dt:
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04/23/1999
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Title:
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TRENCH STORAGE DYNAMIC RANDOM ACCESS MEMORY CELL WITH VERTICAL TRANSFER DEVICE
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09302902
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Filing Dt:
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04/30/1999
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Title:
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IMPEDANCE CONTROL USING FUSES
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09422367
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Filing Dt:
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10/21/1999
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Title:
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METHOD AND APPARATUS FOR PROCESS INDEPENDENT CLOCK SIGNAL DISTRIBUTION
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09458877
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Filing Dt:
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12/10/1999
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Title:
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CONDUCTIVE LINE FEATURES FOR ENHANCED RELIABILITY OF MULTI-LAYER CERAMIC SUBSTRATES
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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09501393
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Filing Dt:
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02/09/2000
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Title:
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Write through function for a memory
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09524661
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Filing Dt:
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03/13/2000
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Title:
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Multi-ported memory with asynchronous and synchronous protocol
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09526198
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Filing Dt:
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03/15/2000
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Title:
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MACRO DESIGN TECHNIQUES TO ACCOMMODATE CHIP LEVEL WIRING AND CIRCUIT PLACEMENT ACROSS THE MACRO
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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09574186
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Filing Dt:
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05/18/2000
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Title:
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METHOD AND APPARATUS FOR PRESERVING THE CONTENTS OF SYNCHRONOUS DRAM THROUGH SYSTEM RESET
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09588202
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Filing Dt:
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06/06/2000
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Title:
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AUTOMATIC OFF-CHIP DRIVER ADJUSTMENT BASED ON LOAD CHARACTERISTICS
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09589922
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Filing Dt:
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06/07/2000
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Title:
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Impedance control using fuses
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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09615767
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Filing Dt:
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07/13/2000
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Title:
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UNIVERSAL BOOT CODE FOR A COMPUTER NETWORK
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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09617558
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Filing Dt:
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07/17/2000
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Title:
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PROGRAMMABLE COMPENSATED DELAY FOR DDR SDRAM INTERFACE USING PROGRAMMABLE DELAY LOOP FOR REFERENCE CALIBRATION
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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09669117
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Filing Dt:
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09/25/2000
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Title:
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COMPILABLE ADDRESS MAGNITUDE COMPARATOR FOR MEMORY ARRAY SELF-TESTING
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09682638
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Filing Dt:
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10/01/2001
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Title:
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EMBEDDED CAM TEST STRUCTURE FOR FULLY TESTING ALL MATCHLINES
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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09683808
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Filing Dt:
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02/19/2002
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Publication #:
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Pub Dt:
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08/21/2003
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Title:
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REDUNDANT ANTIFUSE SEGMENTS FOR IMPROVED PROGRAMMING EFFICIENCY
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09690674
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10/17/2000
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Title:
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SOI HYBRID STRUCTURE WITH SELECTIVE EPITAXIAL GROWTH OF SILICON
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09731147
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Filing Dt:
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12/05/2000
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Publication #:
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Pub Dt:
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08/01/2002
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Title:
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METHOD AND APPARATUS FOR INITIALIZING AN INTEGRATED CIRCUIT USING COMPRESSED DATA FROM A REMOTE FUSEBOX
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09733295
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Filing Dt:
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12/08/2000
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Publication #:
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Pub Dt:
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08/15/2002
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Title:
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METHOD AND APPARATUS FOR TESTING A WRITE FUNCTION OF A DUAL-PORT STATIC MEMORY CELL
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Patent #:
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Issue Dt:
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02/18/2003
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Application #:
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09737012
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Filing Dt:
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12/14/2000
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Publication #:
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Pub Dt:
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08/15/2002
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Title:
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METHOD FOR SUPPLY VOLTAGE DROP ANALYSIS DURING PLACEMENT PHASE OF CHIP DESIGN
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09757107
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01/08/2001
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Publication #:
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Pub Dt:
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07/11/2002
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Title:
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LINEAR VOLTAGE CONTROLLED OSCILLATOR TRANSCONDUCTOR WITH GAIN COMPENSATION
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09757267
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Filing Dt:
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01/09/2001
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Publication #:
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Pub Dt:
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07/11/2002
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Title:
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PROGRAMMABLE LATCH DEVICE WITH INTEGRATED PROGRAMMABLE ELEMENT
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09765035
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Filing Dt:
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01/17/2001
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Title:
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INTEGRATED FUSE LATCH AND SHIFT REGISTER FOR EFFICIENT PROGRAMMING AND FUSE READOUT
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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09768122
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Filing Dt:
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01/23/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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METHOD FOR GUARANTEEING A MINIMUM DATA STROBE VALID WINDOW AND A MINIMUM DATA VALID WINDOW FOR DDR MEMORY DEVICES
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Patent #:
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Issue Dt:
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06/22/2004
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09791003
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02/22/2001
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Publication #:
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Pub Dt:
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08/22/2002
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Title:
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SYSTEM AND METHOD TO PREDETERMINE A BITMAP OF A SELF-TESTED EMBEDDED ARRAY
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Issue Dt:
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03/11/2003
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Application #:
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09795610
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02/27/2001
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Publication #:
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Pub Dt:
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08/29/2002
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Title:
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INTRINSIC DUAL GATE OXIDE MOSFET USING A DAMASCENE GATE PROCESS
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Patent #:
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Issue Dt:
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08/08/2006
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09805027
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03/12/2001
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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COPPER TO ALUMINUM INTERLAYER INTERCONNECT USING STUD AND VIA LINER
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Issue Dt:
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08/13/2002
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Application #:
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09805420
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Filing Dt:
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03/13/2001
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Title:
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CLOCKED MEMORY DEVICE THAT INCLUDES A PROGRAMMING MECHANISM FOR SETTING WRITE RECOVERY TIME AS A FUNCTION OF THE INPUT CLOCK
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Patent #:
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Issue Dt:
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12/03/2002
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09810133
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Filing Dt:
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03/16/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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CROSSTALK SUPPRESSION IN DIFFERENTIAL AC COUPLED MULTICHANNEL IC AMPLIFIERS
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Issue Dt:
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10/22/2002
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09810763
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03/16/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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SUBSTITUTION OF NON-MINIMUM GROUNDRULE CELLS FOR NON-CRITICAL MINIMUM GROUNDRULE CELLS TO INCREASE YIELD
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Issue Dt:
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06/15/2004
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09827073
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04/05/2001
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Publication #:
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Pub Dt:
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11/21/2002
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Title:
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ULTRA HIGH-SPEED DDP-SRAM CACHE
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Patent #:
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Issue Dt:
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12/14/2004
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Application #:
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09862427
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Filing Dt:
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05/21/2001
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Publication #:
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Pub Dt:
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11/21/2002
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Title:
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SYSTEM AND METHOD FOR ANALYZING POWER DISTRIBUTION USING STATIC TIMING ANALYSIS
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09870559
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Filing Dt:
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05/31/2001
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Title:
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STABILIZED DIRECT SENSING MEMORY ARCHITECTURE
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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09870623
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Filing Dt:
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05/31/2001
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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METHOD AND APPARATUS FOR INTERFACE SIGNALING USING SINGLE-ENDED AND DIFFERENTIAL DATA SIGNALS
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09870755
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Filing Dt:
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05/31/2001
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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SINGLE BITLINE DIRECT SENSING ARCHITECTURE FOR HIGH SPEED MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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09885853
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Filing Dt:
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06/20/2001
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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EXTENSION OF FATIGUE LIFE FOR C4 SOLDER BALL TO CHIP CONNECTION
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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09887792
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Filing Dt:
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06/22/2001
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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PROCESS INDEPENDENT SOURCE SYNCHRONOUS DATA CAPTURE APPARATUS AND METHOD
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09892396
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Filing Dt:
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06/27/2001
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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SAVING CONTENT ADDRESSABLE MEMORY POWER THROUGH CONDITIONAL COMPARISONS
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Patent #:
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Issue Dt:
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12/21/2004
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Application #:
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09907387
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Filing Dt:
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07/17/2001
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Publication #:
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Pub Dt:
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01/23/2003
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Title:
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02/11/2003
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09917059
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07/27/2001
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Pub Dt:
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01/30/2003
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Title:
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SENSE AMPLIFIER THRESHOLD COMPENSATION
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Patent #:
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Issue Dt:
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11/08/2005
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09918809
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07/31/2001
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Publication #:
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Pub Dt:
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02/06/2003
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Title:
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ADAPTIVE PHASE LOCKED LOOP
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09974986
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Filing Dt:
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10/11/2001
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Title:
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INTERLEAVED FEEDFORWARD VCO AND PLL
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Patent #:
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Issue Dt:
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03/25/2003
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09977423
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10/15/2001
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Publication #:
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04/17/2003
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Title:
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METHOD AND RING OSCILLATOR FOR EVALUATING DYNAMIC CIRCUITS
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01/31/2006
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09996053
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11/28/2001
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09/26/2002
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Title:
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ANALOG UNIDIRECTIONAL SERIAL LINK ARCHITECTURE
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11/18/2003
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10059863
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01/30/2002
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07/31/2003
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Title:
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HIGH RELIABILITY CONTENT-ADDRESSABLE MEMORY USING SHADOW CONTENT-ADDRESSABLE MEMORY
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08/17/2004
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10063212
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03/29/2002
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10/02/2003
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Title:
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COMPLEMENTARY TWO TRANSISTOR ROM CELL
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01/24/2006
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10063394
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04/18/2002
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10/23/2003
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Title:
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ON CHIP TIMING ADJUSTMENT IN MULTI-CHANNEL FAST DATA TRANSFER
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11/23/2004
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10063427
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04/23/2002
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10/23/2003
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Title:
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PHYSICAL DESIGN CHARACTERIZATION SYSTEM
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Patent #:
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Issue Dt:
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12/11/2007
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10063495
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04/30/2002
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Pub Dt:
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10/30/2003
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Title:
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TESTING OF ECC MEMORIES
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Patent #:
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Issue Dt:
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12/12/2006
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10063497
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Filing Dt:
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04/30/2002
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Publication #:
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Pub Dt:
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10/30/2003
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Title:
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OPTIMIZED ECC/REDUNDANCY FAULT RECOVERY
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Patent #:
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05/04/2004
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10063504
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05/01/2002
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Publication #:
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Pub Dt:
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11/06/2003
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Title:
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GLOBAL VOLTAGE BUFFER FOR VOLTAGE ISLANDS
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Issue Dt:
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03/28/2006
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10063859
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05/20/2002
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11/20/2003
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Title:
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METHOD AND APPARATUS FOR PROVIDING NOISE SUPPRESSION IN AN INTEGRATED CIRCUIT
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09/21/2004
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10064921
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08/29/2002
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Pub Dt:
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03/04/2004
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Title:
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APPARATUS FOR REDUCING SOFT ERRORS IN DYNAMIC CIRCUITS
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Patent #:
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08/16/2005
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10065475
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10/22/2002
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Pub Dt:
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04/22/2004
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Title:
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TERMINATING RESISTOR DRIVER FOR HIGH SPEED DATA COMMUNICATION
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06/13/2006
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10072346
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02/06/2002
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08/08/2002
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Title:
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ADDRESS WRAP FUNCTION FOR ADDRESSABLE MEMORY DEVICES
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11/18/2003
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10078174
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02/15/2002
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08/21/2003
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Title:
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UNIQUE FEATURE DESIGN ENABLING STRUCTURAL INTEGRITY FOR ADVANCED LOW K SEMICONDUCTOR CHIPS
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03/02/2004
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10116813
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04/05/2002
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08/22/2002
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Title:
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METHOD AND APPARATUS FOR PROCESS INDEPENDENT CLOCK SIGNAL DISTRIBUTION
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12/02/2003
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10140549
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05/07/2002
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11/13/2003
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Title:
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SPLIT LOCAL AND CONTINUOUS BITLINE FOR FAST DOMINO READ SRAM
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06/21/2005
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10176233
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06/20/2002
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Pub Dt:
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12/25/2003
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Title:
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METHOD AND APPARATUS TO MAKE A SEMICONDUCTOR CHIP SUSCEPTIBLE TO RADIATION FAILURE
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07/19/2005
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10199788
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07/19/2002
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01/22/2004
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Title:
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METHOD AND APPARATUS OF LOCAL WORD-LINE REDUNDANCY IN CAM
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11/23/2004
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10235435
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09/04/2002
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03/04/2004
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Title:
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REDUNDANT CONFIGURABLE VCSEL LASER ARRAY OPTICAL LIGHT SOURCE
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01/10/2006
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10248302
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01/07/2003
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07/08/2004
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Title:
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SIGNAL BALANCING BETWEEN VOLTAGE DOMAINS
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11/30/2004
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10249273
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03/27/2003
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09/30/2004
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Title:
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SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY DEVICE HAVING MEMORY COMMAND CANCEL FUNCTION
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05/04/2004
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10249311
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03/31/2003
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Title:
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TRI-STATE DELAY BOOST
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01/20/2009
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10249331
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04/01/2003
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10/07/2004
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METHOD FOR PERFORMING A COMMAND CANCEL FUNCTION IN A DRAM
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06/08/2004
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10249347
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04/02/2003
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Title:
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GAIN CELL STRUCTURE WITH DEEP TRENCH CAPACITOR
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05/10/2005
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10249545
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04/17/2003
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10/21/2004
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REFERENCE CURRENT GENERATION SYSTEM AND METHOD
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11/30/2004
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10249684
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04/30/2003
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11/04/2004
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POWER REDUCTION BY STAGE IN INTEGRATED CIRCUIT
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01/20/2004
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10249795
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05/08/2003
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Title:
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HIGH SPEED FIR TRANSMITTER
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