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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:028084/0627   Pages: 10
Recorded: 04/20/2012
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 59
1
Patent #:
5615159
Issue Dt:
03/25/1997
Application #:
08563505
Filing Dt:
11/28/1995
Title:
MEMORY SYSTEM WITH NON-VOLATILE DATA STORAGE UNIT AND METHOD OF INITIALIZING SAME
2
Patent #:
5813590
Issue Dt:
09/29/1998
Application #:
08574156
Filing Dt:
12/18/1995
Title:
EXTENDED TRAVEL WIRE BONDING MACHINE
3
Patent #:
5677885
Issue Dt:
10/14/1997
Application #:
08751072
Filing Dt:
11/15/1996
Title:
MEMORY SYSTEM WITH NON-VOLATILE DATA STORAGE UNIT AND METHOD OF INITIALIZING SAME
4
Patent #:
5976964
Issue Dt:
11/02/1999
Application #:
08840604
Filing Dt:
04/22/1997
Title:
METHOD OF IMPROVING INTERCONNECT OF SEMICINDUCTOR DEVICE BY UTILIZING A FLATTENED BALL BOND
5
Patent #:
6021459
Issue Dt:
02/01/2000
Application #:
08847641
Filing Dt:
04/23/1997
Title:
MEMORY SYSTEM HAVING FLEXIBLE BUS STRUCTURE AND METHOD
6
Patent #:
6015079
Issue Dt:
01/18/2000
Application #:
08905183
Filing Dt:
08/04/1997
Title:
A POSITIONING DEVICE FOR CONTROLLING THE POSITION OF A WORKPIECE IN A HORIZONTAL PLANE
7
Patent #:
6107109
Issue Dt:
08/22/2000
Application #:
08993965
Filing Dt:
12/18/1997
Title:
METHOD FOR FABRICATING A SEMICONDUCTOR INTERCONNECT WITH LASER MACHINED ELECTRICAL PATHS THROUGH SUBSTRATE
8
Patent #:
6196445
Issue Dt:
03/06/2001
Application #:
09208279
Filing Dt:
12/08/1998
Title:
A METHOD FOR POSITIONING THE BOND HEAD IN A WIRE BONDING MACHINE
9
Patent #:
6034440
Issue Dt:
03/07/2000
Application #:
09234140
Filing Dt:
01/19/1999
Title:
METHOD OF IMPROVING INTERCONNECT OF SEMICONDUCTOR DEVICES BY UTILIZING A FLATTENED BALL BOND
10
Patent #:
6223967
Issue Dt:
05/01/2001
Application #:
09241467
Filing Dt:
02/01/1999
Title:
EXTENDED TRAVEL WIRE BONDING MACHINE
11
Patent #:
6212123
Issue Dt:
04/03/2001
Application #:
09351879
Filing Dt:
07/13/1999
Title:
MEMORY SYSTEM HAVING FLEXIBLE BUS STRUCTURE AND METHOD
12
Patent #:
6294837
Issue Dt:
09/25/2001
Application #:
09385606
Filing Dt:
08/30/1999
Title:
SEMICONDUCTOR INTERCONNECT HAVING LASER MACHINED CONTACTS
13
Patent #:
6418070
Issue Dt:
07/09/2002
Application #:
09388566
Filing Dt:
09/02/1999
Title:
MEMORY DEVICE TESTER AND METHOD FOR TESTING REDUCED POWER STATES
14
Patent #:
6165887
Issue Dt:
12/26/2000
Application #:
09391638
Filing Dt:
09/07/1999
Title:
METHOD OF IMPROVING INTERCONNECT OF SEMICONDUCTOR DEVICES BY USING A FLATTENED BALL BOND
15
Patent #:
6420256
Issue Dt:
07/16/2002
Application #:
09684448
Filing Dt:
10/06/2000
Title:
METHOD OF IMPROVING INTERCONNECT OF SEMICONDUCTOR DEVICES BY USING A FLATTENED BALL BOND
16
Patent #:
6276594
Issue Dt:
08/21/2001
Application #:
09695110
Filing Dt:
10/23/2000
Title:
A METHOD FOR POSITIONING THE BOND HEAD IN A WIRE BONDING MACHINE
17
Patent #:
6253990
Issue Dt:
07/03/2001
Application #:
09695111
Filing Dt:
10/23/2000
Title:
Method for positioning the bond head in a wire bonding machine
18
Patent #:
6321970
Issue Dt:
11/27/2001
Application #:
09695368
Filing Dt:
10/23/2000
Title:
wire bonding machine
19
Patent #:
6253991
Issue Dt:
07/03/2001
Application #:
09695376
Filing Dt:
10/23/2000
Title:
A METHID FOR POSITIONING THE BOND HEAD IN A WIRE BONDING MACHINE
20
Patent #:
6396729
Issue Dt:
05/28/2002
Application #:
09711413
Filing Dt:
11/13/2000
Title:
Memory system having flexible bus structure and method
21
Patent #:
6567335
Issue Dt:
05/20/2003
Application #:
09711416
Filing Dt:
11/13/2000
Title:
MEMORY SYSTEM HAVING FLEXIBLE BUS STRUCTURE AND METHOD
22
Patent #:
6515936
Issue Dt:
02/04/2003
Application #:
09711417
Filing Dt:
11/13/2000
Title:
MEMORY SYSTEM HAVING FLEXIBLE BUS STRUCTURE AND METHOD
23
Patent #:
6320815
Issue Dt:
11/20/2001
Application #:
09711623
Filing Dt:
11/13/2000
Title:
Momory system having flexible bus structure and method
24
Patent #:
6353571
Issue Dt:
03/05/2002
Application #:
09711812
Filing Dt:
11/13/2000
Title:
Memory system having flexible bus structure and method
25
Patent #:
6833613
Issue Dt:
12/21/2004
Application #:
09961646
Filing Dt:
09/25/2001
Title:
SEMICONDUCTOR INTERCONNECT HAVING LASER MACHINED CONTACTS
26
Patent #:
6620731
Issue Dt:
09/16/2003
Application #:
10035355
Filing Dt:
01/04/2002
Title:
METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS AND INTERCONNECTS WITH CONTACTS ON OPPOSING SIDES
27
Patent #:
6674677
Issue Dt:
01/06/2004
Application #:
10166887
Filing Dt:
06/12/2002
Publication #:
US20020149981
Pub Dt:
10/17/2002
Title:
MEMORY DEVICE TESTER AND METHOD FOR TESTING REDUCED POWER STATES
28
Patent #:
6775192
Issue Dt:
08/10/2004
Application #:
10167817
Filing Dt:
06/12/2002
Publication #:
US20020190708
Pub Dt:
12/19/2002
Title:
MEMORY DEVICE TESTER AND METHOD FOR TESTING REDUCED POWER STATES
29
Patent #:
6914843
Issue Dt:
07/05/2005
Application #:
10170561
Filing Dt:
06/12/2002
Publication #:
US20020149982
Pub Dt:
10/17/2002
Title:
MEMORY DEVICE TESTER AND METHOD FOR TESTING REDUCED POWER STATES
30
Patent #:
6624059
Issue Dt:
09/23/2003
Application #:
10197271
Filing Dt:
07/15/2002
Publication #:
US20020177296
Pub Dt:
11/28/2002
Title:
METHOD OF IMPROVING INTERCONNECT OF SEMICONDUCTOR DEVICES BY UTILIZING A FLATTENED BALL BOND
31
Patent #:
6903443
Issue Dt:
06/07/2005
Application #:
10316349
Filing Dt:
12/11/2002
Publication #:
US20030080408
Pub Dt:
05/01/2003
Title:
Semiconductor component and interconnect having conductive members and contacts on opposing sides
32
Patent #:
6998344
Issue Dt:
02/14/2006
Application #:
10815083
Filing Dt:
03/31/2004
Publication #:
US20040178491
Pub Dt:
09/16/2004
Title:
METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS BY FORMING CONDUCTIVE MEMBERS USING SOLDER
33
Patent #:
6952054
Issue Dt:
10/04/2005
Application #:
10820674
Filing Dt:
04/08/2004
Publication #:
US20040188824
Pub Dt:
09/30/2004
Title:
Semiconductor package having interconnect with conductive members
34
Patent #:
7669027
Issue Dt:
02/23/2010
Application #:
10922299
Filing Dt:
08/19/2004
Publication #:
US20060041730
Pub Dt:
02/23/2006
Title:
MEMORY COMMAND DELAY BALANCING IN A DAISY-CHAINED MEMORY TOPOLOGY
35
Patent #:
7164611
Issue Dt:
01/16/2007
Application #:
10973208
Filing Dt:
10/26/2004
Publication #:
US20060087882
Pub Dt:
04/27/2006
Title:
DATA RETENTION KILL FUNCTION
36
Patent #:
7161866
Issue Dt:
01/09/2007
Application #:
11173307
Filing Dt:
07/01/2005
Publication #:
US20050243638
Pub Dt:
11/03/2005
Title:
MEMORY DEVICE TESTER AND METHOD FOR TESTING REDUCED POWER STATES
37
Patent #:
7966450
Issue Dt:
06/21/2011
Application #:
11219324
Filing Dt:
09/01/2005
Publication #:
US20070050540
Pub Dt:
03/01/2007
Title:
NON-VOLATILE HARD DISK DRIVE CACHE SYSTEM AND METHOD
38
Patent #:
7564721
Issue Dt:
07/21/2009
Application #:
11442514
Filing Dt:
05/25/2006
Publication #:
US20070274134
Pub Dt:
11/29/2007
Title:
METHOD AND APPARATUS FOR IMPROVING STORAGE PERFORMANCE USING A BACKGROUND ERASE
39
Patent #:
7477554
Issue Dt:
01/13/2009
Application #:
11490215
Filing Dt:
07/20/2006
Publication #:
US20060294291
Pub Dt:
12/28/2006
Title:
DATA RETENTION KILL FUNCTION
40
Patent #:
7466600
Issue Dt:
12/16/2008
Application #:
11499231
Filing Dt:
08/03/2006
Publication #:
US20080031061
Pub Dt:
02/07/2008
Title:
SYSTEM AND METHOD FOR INITIATING A BAD BLOCK DISABLE PROCESS IN A NON-VOLATILE MEMORY
41
Patent #:
7564722
Issue Dt:
07/21/2009
Application #:
11656578
Filing Dt:
01/22/2007
Publication #:
US20080177923
Pub Dt:
07/24/2008
Title:
MEMORY SYSTEM AND METHOD HAVING VOLATILE AND NON-VOLATILE MEMORY DEVICES AT SAME HIERARCHICAL LEVEL
42
Patent #:
7791952
Issue Dt:
09/07/2010
Application #:
11699954
Filing Dt:
01/30/2007
Publication #:
US20080183950
Pub Dt:
07/31/2008
Title:
MEMORY DEVICE ARCHITECTURES AND OPERATION
43
Patent #:
7925844
Issue Dt:
04/12/2011
Application #:
11947596
Filing Dt:
11/29/2007
Publication #:
US20090141564
Pub Dt:
06/04/2009
Title:
MEMORY REGISTER ENCODING SYSTEMS AND METHODS
44
Patent #:
8060719
Issue Dt:
11/15/2011
Application #:
12127945
Filing Dt:
05/28/2008
Publication #:
US20090300269
Pub Dt:
12/03/2009
Title:
HYBRID MEMORY MANAGEMENT
45
Patent #:
7692984
Issue Dt:
04/06/2010
Application #:
12330359
Filing Dt:
12/08/2008
Publication #:
US20090091994
Pub Dt:
04/09/2009
Title:
SYSTEM AND METHOD FOR INITIATING A BAD BLOCK DISABLE PROCESS IN A NON-VOLATILE MEMORY
46
Patent #:
7751263
Issue Dt:
07/06/2010
Application #:
12352485
Filing Dt:
01/12/2009
Publication #:
US20090153181
Pub Dt:
06/18/2009
Title:
DATA RETENTION KILL FUNCTION
47
Patent #:
7742344
Issue Dt:
06/22/2010
Application #:
12491846
Filing Dt:
06/25/2009
Publication #:
US20090257284
Pub Dt:
10/15/2009
Title:
METHOD AND APPARATUS FOR IMPROVING STORAGE PERFORMANCE USING A BACKGROUND ERASE
48
Patent #:
7778092
Issue Dt:
08/17/2010
Application #:
12497400
Filing Dt:
07/02/2009
Publication #:
US20090265509
Pub Dt:
10/22/2009
Title:
MEMORY SYSTEM AND METHOD HAVING VOLATILE AND NON-VOLATILE MEMORY DEVICES AT SAME HIERARCHICAL LEVEL
49
Patent #:
7908451
Issue Dt:
03/15/2011
Application #:
12689495
Filing Dt:
01/19/2010
Publication #:
US20100122059
Pub Dt:
05/13/2010
Title:
MEMORY COMMAND DELAY BALANCING IN A DAISY-CHAINED MEMORY TOPOLOGY
50
Patent #:
8023344
Issue Dt:
09/20/2011
Application #:
12827686
Filing Dt:
06/30/2010
Publication #:
US20100265781
Pub Dt:
10/21/2010
Title:
DATA RETENTION KILL FUNCTION
51
Patent #:
7916553
Issue Dt:
03/29/2011
Application #:
12830113
Filing Dt:
07/02/2010
Publication #:
US20100306461
Pub Dt:
12/02/2010
Title:
MEMORY SYSTEM AND METHOD HAVING VOLATILE AND NON-VOLATILE MEMORY DEVICES AT SAME HIERARCHICAL LEVEL
52
Patent #:
7990775
Issue Dt:
08/02/2011
Application #:
12875763
Filing Dt:
09/03/2010
Publication #:
US20100329038
Pub Dt:
12/30/2010
Title:
METHODS OF OPERATING MEMORY DEVICES INCLUDING DIFFERENT SETS OF LOGICAL ERASE BLOCKS
53
Patent #:
8166268
Issue Dt:
04/24/2012
Application #:
13033364
Filing Dt:
02/23/2011
Publication #:
US20110145522
Pub Dt:
06/16/2011
Title:
MEMORY COMMAND DELAY BALANCING IN A DAISY-CHAINED MEMORY TOPOLOGY
54
Patent #:
8248861
Issue Dt:
08/21/2012
Application #:
13051329
Filing Dt:
03/18/2011
Publication #:
US20110167207
Pub Dt:
07/07/2011
Title:
MEMORY SYSTEM AND METHOD HAVING VOLATILE AND NON-VOLATILE MEMORY DEVICES AT SAME HIERARCHICAL LEVEL
55
Patent #:
8156291
Issue Dt:
04/10/2012
Application #:
13074917
Filing Dt:
03/29/2011
Publication #:
US20110179221
Pub Dt:
07/21/2011
Title:
MEMORY REGISTER ENCODING SYSTEMS AND METHODS
56
Patent #:
8850112
Issue Dt:
09/30/2014
Application #:
13108805
Filing Dt:
05/16/2011
Publication #:
US20110219167
Pub Dt:
09/08/2011
Title:
NON-VOLATILE HARD DISK DRIVE CACHE SYSTEM AND METHOD
57
Patent #:
8199587
Issue Dt:
06/12/2012
Application #:
13195308
Filing Dt:
08/01/2011
Publication #:
US20110286272
Pub Dt:
11/24/2011
Title:
MEMORY DEVICES AND THEIR OPERATION WITH DIFFERENT SETS OF LOGICAL ERASE BLOCKS
58
Patent #:
8565035
Issue Dt:
10/22/2013
Application #:
13236394
Filing Dt:
09/19/2011
Publication #:
US20120008440
Pub Dt:
01/12/2012
Title:
DATA RETENTION KILL FUNCTION
59
Patent #:
8296510
Issue Dt:
10/23/2012
Application #:
13295616
Filing Dt:
11/14/2011
Publication #:
US20120059992
Pub Dt:
03/08/2012
Title:
HYBRID MEMORY MANAGEMENT
Assignor
1
MICRON TECHNOLOGY, INC.
Exec Dt:
03/16/2012
Assignee
1
ROUND ROCK RESEARCH, LLC
P. O. BOX 1042
MOUNT KISCO, NEW YORK 10549
Correspondence name and address
RICHARD J. BOTOS
LERNER, DAVID, LITTENBERG, KRUMHOLZ ET AL.
600 SOUTH AVENUE WEST
WESTFIELD, NJ 07090

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