Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 029551/0629 | |
| Pages: | 2 |
| | Recorded: | 01/02/2013 | | |
| Attorney Dkt #: | FIS920120225US1 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13732455
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Filing Dt:
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01/02/2013
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Publication #:
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Pub Dt:
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07/03/2014
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Title:
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CONCURRENTLY FORMING NFET AND PFET GATE DIELECTRIC LAYERS
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Assignee
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| P.O. BOX 309 |
| UGLAND HOUSE |
| GRAND CAYMAN, CAYMAN ISLANDS KY1-1104 |
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Correspondence name and address
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IBM - FISHKILL DRAFTING CENTER
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2070 ROUTE 52
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M/D 0482
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HOPEWELL JUNCTION, NY 12533
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