Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 024990/0632 | |
| Pages: | 8 |
| | Recorded: | 09/16/2010 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09056555
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Filing Dt:
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04/07/1998
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Title:
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METHOD OF FORMING SEMICONDUCTOR DEVICE WITH LDD STRUCTURE
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09364366
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Filing Dt:
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07/30/1999
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Title:
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METHOD OF MAKING INTEGRATED CIRCUIT CAPACITOR INCLUDING TAPERED PLUG
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09364603
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Filing Dt:
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07/30/1999
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Title:
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INTEGRATED CIRCUIT CAPACITOR INCLUDING TAPERED PLUG
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09481992
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Filing Dt:
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01/11/2000
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Title:
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METHOD OF MAKING A GRADED GROWN, HIGH QUALITY OXIDE LAYER FOR A SEMICONDUCTOR DEVICE
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Assignee
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| 1110 AMERICAN PARKWAY NE |
| ALLENTOWN, PENNSYLVANIA 18109 |
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Correspondence name and address
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PATRICIA M. LOTT
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400 CONNELL DRIVE
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BERKELEY HEIGHTS, NJ 07922
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