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OPTIMIZING LOCATIONS OF PINS FOR BLOCKS IN A HIERARCHICAL PHYSICAL DESIGN BY USING PHYSICAL DESIGN INFORMATION OF A PRIOR HIERARCHICAL PHYSICAL DESIGN
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Patent #:
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Issue Dt:
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04/01/2008
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Application #:
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10856268
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Filing Dt:
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05/27/2004
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Title:
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FLOW DEFINITION LANGUAGE FOR DESIGNING INTEGRATED CIRCUIT IMPLEMENTATION FLOWS
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Patent #:
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Issue Dt:
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04/10/2007
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Application #:
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10861247
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Filing Dt:
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06/04/2004
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Title:
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ASYNCHRONOUS CONTROL OF MEMORY SELF TEST
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Patent #:
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Issue Dt:
|
07/03/2007
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Application #:
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10861812
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Filing Dt:
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06/04/2004
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Title:
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REDUNDANTLY TIED METAL FILL FOR IR-DROP AND LAYOUT DENSITY OPTIMIZATION
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Patent #:
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Issue Dt:
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02/26/2008
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Application #:
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10880649
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Filing Dt:
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06/29/2004
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Title:
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METHOD OF USING STRONGLY COUPLED COMPONENTS TO ESTIMATE INTEGRATED CIRCUIT PERFORMANCE
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Patent #:
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Issue Dt:
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03/04/2008
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Application #:
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10881195
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Filing Dt:
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06/29/2004
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Title:
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METHOD OF ESTIMATING PERFORMANCE OF INTEGRATED CIRCUIT DESIGNS BY FINDING SCALARS FOR STRONGLY COUPLED COMPONENTS
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Patent #:
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Issue Dt:
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02/14/2006
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Application #:
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10881832
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Filing Dt:
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06/29/2004
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Title:
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METHOD OF VECTOR GENERATION FOR ESTIMATING PERFORMANCE OF INTEGRATED CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
|
10/03/2006
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Application #:
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10882003
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Filing Dt:
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06/29/2004
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Title:
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METHOD OF ESTIMATING PERFORMANCE OF INTEGRATED CIRCUIT DESIGNS USING STATE POINT IDENTIFICATION
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Patent #:
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Issue Dt:
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11/25/2008
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Application #:
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11021278
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Filing Dt:
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12/22/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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CIRCUIT OPTIMIZATION WITH POSYNOMIAL FUNCTION F HAVING AN EXPONENT OF A FIRST DESIGN PARAMETER
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Patent #:
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Issue Dt:
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11/25/2008
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Application #:
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11021278
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Filing Dt:
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12/22/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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CIRCUIT OPTIMIZATION WITH POSYNOMIAL FUNCTION F HAVING AN EXPONENT OF A FIRST DESIGN PARAMETER
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Patent #:
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Issue Dt:
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03/18/2008
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Application #:
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11048287
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Filing Dt:
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01/31/2005
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Title:
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PARAMETRIC TIMING ANALYSIS
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Patent #:
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Issue Dt:
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08/05/2008
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Application #:
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11140914
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Filing Dt:
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06/01/2005
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Publication #:
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Pub Dt:
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12/01/2005
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Title:
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METHODS AND SYSTEMS FOR MIXED-MODE PHYSICAL SYNTHESIS IN ELECTRONIC DESIGN AUTOMATION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11141386
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Filing Dt:
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06/01/2005
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Publication #:
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Pub Dt:
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12/01/2005
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Title:
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Rule-based design consultant and method for integrated circuit design
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11262736
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Filing Dt:
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11/01/2005
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Publication #:
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Pub Dt:
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03/09/2006
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Title:
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Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11264919
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Filing Dt:
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11/01/2005
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Publication #:
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Pub Dt:
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05/25/2006
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Title:
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Sensitivity-current-based model for equivalent waveform propagation in the presence of noise for static timing analysis
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Patent #:
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Issue Dt:
|
10/07/2008
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Application #:
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11372557
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Filing Dt:
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03/09/2006
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Title:
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LITHOGRAPHICALLY OPTIMIZED PLACEMENT TOOL
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Patent #:
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Issue Dt:
|
11/25/2008
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Application #:
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11451905
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Filing Dt:
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06/12/2006
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Title:
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AGGREGATE SENSITIVITY FOR STATISTICAL STATIC TIMING ANALYSIS
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Patent #:
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Issue Dt:
|
11/04/2008
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Application #:
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11452542
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Filing Dt:
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06/13/2006
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Publication #:
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Pub Dt:
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01/04/2007
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Title:
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SIGNAL FLOW DRIVEN CIRCUIT ANALYSIS AND PARTITIONING TECHNIQUE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11734757
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Filing Dt:
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04/12/2007
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Publication #:
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Pub Dt:
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10/18/2007
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Title:
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Placement-Driven Physical-Hierarchy Generation
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11748416
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Filing Dt:
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05/14/2007
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Publication #:
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Pub Dt:
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11/15/2007
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Title:
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Relative Floorplanning For Improved Integrated Circuit Design
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Patent #:
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Issue Dt:
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10/29/2013
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Application #:
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11781043
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Filing Dt:
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07/20/2007
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Publication #:
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Pub Dt:
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02/28/2008
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Title:
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LITHOGRAPHY AWARE LEAKAGE ANALYSIS
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Patent #:
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Issue Dt:
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06/25/2013
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Application #:
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11781054
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Filing Dt:
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07/20/2007
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Publication #:
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Pub Dt:
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02/28/2008
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Title:
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LITHOGRAPHY AWARE TIMING ANALYSIS
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Patent #:
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Issue Dt:
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08/24/2010
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Application #:
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11900749
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Filing Dt:
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09/12/2007
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Publication #:
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Pub Dt:
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03/27/2008
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Title:
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NOVEL OPTIMIZATION FOR CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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04/20/2010
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Application #:
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11900856
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Filing Dt:
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09/12/2007
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Publication #:
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Pub Dt:
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03/20/2008
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Title:
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NOVEL OPTIMIZATION FOR CIRCUIT DESIGN
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Patent #:
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NONE
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Application #:
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11986253
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Filing Dt:
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11/19/2007
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Publication #:
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Pub Dt:
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03/20/2008
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Title:
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Parser for signomial and geometric programs
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Patent #:
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NONE
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Application #:
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12113834
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05/01/2008
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Publication #:
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Pub Dt:
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08/28/2008
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Title:
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METHOD FOR STORING MULTIPLE LEVELS OF DESIGN DATA IN A COMMON DATABASE
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Patent #:
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04/19/2011
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12128554
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05/28/2008
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Pub Dt:
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12/04/2008
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Title:
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METHOD FOR AUTOMATIC CLOCK GATING TO SAVE POWER
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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12128574
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05/28/2008
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Pub Dt:
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12/04/2008
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Title:
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METHOD FOR OPTIMIZED AUTOMATIC CLOCK GATING
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Patent #:
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06/28/2011
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Application #:
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12128919
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05/29/2008
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Title:
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METHOD FOR REPEATED BLOCK TIMING ANALYSIS
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03/26/2013
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12129916
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05/30/2008
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Title:
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METHOD FOR REPEATED BLOCK MODIFICATION FOR CHIP ROUTING
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08/23/2011
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12134849
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06/06/2008
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Title:
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DYNAMIC PUSH FOR TOPOLOGICAL ROUTING OF SEMICONDUCTOR PACKAGES
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08/02/2011
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12135031
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06/06/2008
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Title:
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TIMING ANALYSIS USING STATISTICAL ON-CHIP VARIATION
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Patent #:
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07/31/2012
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12156963
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06/05/2008
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Title:
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MULTI-THREADED GLOBAL ROUTING
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06/07/2011
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12170354
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07/09/2008
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Title:
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METHOD FOR MULTI-CYCLE PATH AND FALSE PATH CLOCK GATING
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11/06/2012
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12195326
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08/20/2008
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Title:
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AUTOMATED CIRCUIT DESIGN USING ACTIVE SET SOLVING PROCESS
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04/22/2014
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12479681
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06/05/2009
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01/14/2010
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Title:
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Structured Placement For Bit Slices
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