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Reel/Frame:	032439/0638			Pages:	39
		Recorded:	03/13/2014
Conveyance:	CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).

Total properties: 1383
Page 12 of 14
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14

Patent #:	7889580	Issue Dt:	02/15/2011	Application #:	12651707	Filing Dt:	01/04/2010
Publication #:	US20100097869	Pub Dt:	04/22/2010
Title:	MEMORY SYSTEM HAVING INCORRUPTED STROBE SIGNALS

Patent #:	8412968	Issue Dt:	04/02/2013	Application #:	12652897	Filing Dt:	01/06/2010
Publication #:	US20100174932	Pub Dt:	07/08/2010
Title:	CIRCUIT, SYSTEM AND METHOD FOR SELECTIVELY TURNING OFF INTERNAL CLOCK DRIVERS

Patent #:	8761186	Issue Dt:	06/24/2014	Application #:	12683731	Filing Dt:	01/07/2010
Publication #:	US20100103928	Pub Dt:	04/29/2010
Title:	TELEPHONE OUTLET WITH PACKET TELEPHONY ADAPTER, AND A NETWORK USING SAME

Patent #:	8209562	Issue Dt:	06/26/2012	Application #:	12684026	Filing Dt:	01/07/2010
Publication #:	US20100122104	Pub Dt:	05/13/2010
Title:	A DOUBLE DATA RATE CONVERTER CIRCUIT INCLUDES A DELAY LOCKED LOOP FOR PROVIDING THE PLURALITY OF CLOCK PHASE SIGNALS

Patent #:	8063658	Issue Dt:	11/22/2011	Application #:	12685365	Filing Dt:	01/11/2010
Publication #:	US20100201397	Pub Dt:	08/12/2010
Title:	TERMINATION CIRCUIT FOR ON-DIE TERMINATION

Patent #:	8472593	Issue Dt:	06/25/2013	Application #:	12685694	Filing Dt:	01/12/2010
Publication #:	US20100189098	Pub Dt:	07/29/2010
Title:	TELEPHONE OUTLET WITH PACKET TELEPHONY ADAPTOR, AND A NETWORK USING SAME

Patent #:	7863954	Issue Dt:	01/04/2011	Application #:	12687541	Filing Dt:	01/14/2010
Publication #:	US20100117698	Pub Dt:	05/13/2010
Title:	TIMING VERNIER USING A DELAY LOCKED LOOP

Patent #:	8324954	Issue Dt:	12/04/2012	Application #:	12691794	Filing Dt:	01/22/2010
Publication #:	US20100117709	Pub Dt:	05/13/2010
Title:	VOLTAGE LEVEL SHIFTER AND BUFFER USING SAME

Patent #:	7911860	Issue Dt:	03/22/2011	Application #:	12698585	Filing Dt:	02/02/2010
Publication #:	US20100135092	Pub Dt:	06/03/2010
Title:	CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS

Patent #:	8144528	Issue Dt:	03/27/2012	Application #:	12699627	Filing Dt:	02/03/2010
Publication #:	US20100202224	Pub Dt:	08/12/2010
Title:	MEMORY WITH DATA CONTROL

Patent #:	7868808	Issue Dt:	01/11/2011	Application #:	12700370	Filing Dt:	02/04/2010
Publication #:	US20100141491	Pub Dt:	06/10/2010
Title:	PHASE-LOCKED LOOP CIRCUITRY USING CHARGE PUMPS WITH CURRENT MIRROR CIRCUITRY

Patent #:	8664748	Issue Dt:	03/04/2014	Application #:	12701122	Filing Dt:	02/05/2010
Publication #:	US20110037148	Pub Dt:	02/17/2011
Title:	PACKAGE-LEVEL INTEGRATED CIRCUIT CONNECTION WITHOUT TOP METAL PADS OR BONDING WIRE

Patent #:	8300488	Issue Dt:	10/30/2012	Application #:	12705040	Filing Dt:	02/12/2010
Publication #:	US20100142304	Pub Dt:	06/10/2010
Title:	DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS WITH TEMPERATURE COMPENSATED SELF-REFRESH

Patent #:	8077527	Issue Dt:	12/13/2011	Application #:	12705345	Filing Dt:	02/12/2010
Publication #:	US20100232236	Pub Dt:	09/16/2010
Title:	SRAM LEAKAGE REDUCTION CIRCUIT

Patent #:	RE43552	Issue Dt:	07/24/2012	Application #:	12709198	Filing Dt:	02/19/2010
Title:	BLOCK PROGRAMMABLE PRIORITY ENCODER IN A CAM

Patent #:	7893737	Issue Dt:	02/22/2011	Application #:	12714670	Filing Dt:	03/01/2010
Publication #:	US20100213994	Pub Dt:	08/26/2010
Title:	CHARGE PUMP FOR PLL/DLL

Patent #:	8045365	Issue Dt:	10/25/2011	Application #:	12715641	Filing Dt:	03/02/2010
Publication #:	US20100157714	Pub Dt:	06/24/2010
Title:	APPARATUS AND METHOD FOR SELF-REFRESHING DYNAMIC RANDOM ACCESS MEMORY CELLS

Patent #:	8126003	Issue Dt:	02/28/2012	Application #:	12718300	Filing Dt:	03/05/2010
Publication #:	US20100223435	Pub Dt:	09/02/2010
Title:	METHOD AND APPARATUS FOR PROVIDING A PACKET BUFFER RANDOM ACCESS MEMORY

Patent #:	8023321	Issue Dt:	09/20/2011	Application #:	12719413	Filing Dt:	03/08/2010
Publication #:	US20100157684	Pub Dt:	06/24/2010
Title:	FLASH MEMORY PROGRAM INHIBIT SCHEME

Patent #:	8058904	Issue Dt:	11/15/2011	Application #:	12724952	Filing Dt:	03/16/2010
Publication #:	US20100171521	Pub Dt:	07/08/2010
Title:	SYSTEM FOR TRANSMISSION LINE TERMINATION BY SIGNAL CANCELLATION

Patent #:	8363797	Issue Dt:	01/29/2013	Application #:	12727375	Filing Dt:	03/19/2010
Publication #:	US20100246786	Pub Dt:	09/30/2010
Title:	TELEPHONE OUTLET FOR IMPLEMENTING A LOCAL AREA NETWORK OVER TELEPHONE LINES AND A LOCAL AREA NETWORK USING SUCH OUTLETS

Patent #:	8000144	Issue Dt:	08/16/2011	Application #:	12732745	Filing Dt:	03/26/2010
Publication #:	US20100182838	Pub Dt:	07/22/2010
Title:	METHOD AND SYSTEM FOR ACCESSING A FLASH MEMORY DEVICE

Patent #:	8474429	Issue Dt:	07/02/2013	Application #:	12735049	Filing Dt:	06/11/2010
Publication #:	US20100251984	Pub Dt:	10/07/2010
Title:	METHOD AND APPARATUS FOR STARTING AN INTERNAL COMBUSTION ENGINE

Patent #:	8035434	Issue Dt:	10/11/2011	Application #:	12750119	Filing Dt:	03/30/2010
Publication #:	US20100182059	Pub Dt:	07/22/2010
Title:	SIMPLIFIED BIAS CIRCUITRY FOR DIFFERENTIAL BUFFER STAGE WITH SYMMETRIC LOADS

Patent #:	8873586	Issue Dt:	10/28/2014	Application #:	12753271	Filing Dt:	04/02/2010
Publication #:	US20100254362	Pub Dt:	10/07/2010
Title:	NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS

Patent #:	8867506	Issue Dt:	10/21/2014	Application #:	12753458	Filing Dt:	04/02/2010
Publication #:	US20100254363	Pub Dt:	10/07/2010
Title:	NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS

Patent #:	7945755	Issue Dt:	05/17/2011	Application #:	12757406	Filing Dt:	04/09/2010
Publication #:	US20100199057	Pub Dt:	08/05/2010
Title:	INDEPENDENT LINK AND BANK SELECTION

Patent #:	8400781	Issue Dt:	03/19/2013	Application #:	12757540	Filing Dt:	04/09/2010
Publication #:	US20110050320	Pub Dt:	03/03/2011
Title:	USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING

Patent #:	8282985	Issue Dt:	10/09/2012	Application #:	12764607	Filing Dt:	04/21/2010
Publication #:	US20100199486	Pub Dt:	08/12/2010
Title:	FLOW-FILL SPACER STRUCTURES FOR FLAT PANEL DISPLAY DEVICE

Patent #:	8503211	Issue Dt:	08/06/2013	Application #:	12770376	Filing Dt:	04/29/2010
Publication #:	US20100296256	Pub Dt:	11/25/2010
Title:	CONFIGURABLE MODULE AND MEMORY SUBSYSTEM

Patent #:	8604593	Issue Dt:	12/10/2013	Application #:	12773340	Filing Dt:	05/04/2010
Publication #:	US20110090004	Pub Dt:	04/21/2011
Title:	RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES

Patent #:	8078821	Issue Dt:	12/13/2011	Application #:	12773531	Filing Dt:	05/04/2010
Publication #:	US20100217928	Pub Dt:	08/26/2010
Title:	SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE

Patent #:	7996485	Issue Dt:	08/09/2011	Application #:	12775696	Filing Dt:	05/07/2010
Publication #:	US20100250699	Pub Dt:	09/30/2010
Title:	METHOD AND APPARATUS FOR REDUCING POOL STARVATION IN A SHARED MEMORY SWITCH

Patent #:	7952923	Issue Dt:	05/31/2011	Application #:	12782047	Filing Dt:	05/18/2010
Publication #:	US20100226174	Pub Dt:	09/09/2010
Title:	MULTIPLE BIT PER CELL NON VOLATILE MEMORY APPARATUS AND SYSTEM HAVING POLARITY CONTROL AND METHOD OF PROGRAMMING SAME

Patent #:	8582382	Issue Dt:	11/12/2013	Application #:	12782911	Filing Dt:	05/19/2010
Publication #:	US20110235426	Pub Dt:	09/29/2011
Title:	MEMORY SYSTEM HAVING A PLURALITY OF SERIALLY CONNECTED DEVICES

Patent #:	8283959	Issue Dt:	10/09/2012	Application #:	12784157	Filing Dt:	05/20/2010
Publication #:	US20100225370	Pub Dt:	09/09/2010
Title:	FREQUENCY-DOUBLING DELAY LOCKED LOOP

Patent #:	8230147	Issue Dt:	07/24/2012	Application #:	12784238	Filing Dt:	05/20/2010
Publication #:	US20100268853	Pub Dt:	10/21/2010
Title:	APPARATUS AND METHOD FOR COMMUNICATING WITH SEMICONDUCTOR DEVICES OF A SERIAL INTERCONNECTION

Patent #:	8045413	Issue Dt:	10/25/2011	Application #:	12785051	Filing Dt:	05/21/2010
Publication #:	US20100232237	Pub Dt:	09/16/2010
Title:	HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY

Patent #:	8842472	Issue Dt:	09/23/2014	Application #:	12785099	Filing Dt:	05/21/2010
Publication #:	US20100226183	Pub Dt:	09/09/2010
Title:	PARTIAL BLOCK ERASE ARCHITECTURE FOR FLASH MEMORY

Patent #:	8533405	Issue Dt:	09/10/2013	Application #:	12812500	Filing Dt:	07/12/2010
Publication #:	US20100306482	Pub Dt:	12/02/2010
Title:	NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Patent #:	8620270	Issue Dt:	12/31/2013	Application #:	12816130	Filing Dt:	06/15/2010
Publication #:	US20110081890	Pub Dt:	04/07/2011
Title:	SYSTEM AND METHOD PROVIDING INTEROPERABILITY BETWEEN CELLULAR AND OTHER WIRELESS SYSTEMS

Patent #:	RE44589	Issue Dt:	11/12/2013	Application #:	12819467	Filing Dt:	06/21/2010
Title:	SINGLE CHIP FRAME BUFFER AND GRAPHICS ACCELERATOR

Patent #:	8504789	Issue Dt:	08/06/2013	Application #:	12823472	Filing Dt:	06/25/2010
Publication #:	US20100327923	Pub Dt:	12/30/2010
Title:	BRIDGING DEVICE HAVING A FREQUENCY CONFIGURABLE CLOCK DOMAIN

Patent #:	8296521	Issue Dt:	10/23/2012	Application #:	12827718	Filing Dt:	06/30/2010
Publication #:	US20100268874	Pub Dt:	10/21/2010
Title:	METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE

Patent #:	7908429	Issue Dt:	03/15/2011	Application #:	12832121	Filing Dt:	07/08/2010
Publication #:	US20100275056	Pub Dt:	10/28/2010
Title:	APPARATUS AND METHOD OF PAGE PROGRAM OPERATION FOR MEMORY DEVICES WITH MIRROR BACK-UP OF DATA

Patent #:	8159893	Issue Dt:	04/17/2012	Application #:	12851884	Filing Dt:	08/06/2010
Publication #:	US20100306569	Pub Dt:	12/02/2010
Title:	DATA FLOW CONTROL IN MULTIPLE INDEPENDENT PORT

Patent #:	7923370	Issue Dt:	04/12/2011	Application #:	12852082	Filing Dt:	08/06/2010
Publication #:	US20100297812	Pub Dt:	11/25/2010
Title:	METHOD FOR STACKING SERIALLY-CONNECTED INTEGRATED CIRCUITS AND MULTI-CHIP DEVICE MADE FROM SAME

Patent #:	NONE	Issue Dt:		Application #:	12855171	Filing Dt:	08/12/2010
Publication #:	US20100325353	Pub Dt:	12/23/2010
Title:	FLASH MEMORY SYSTEM CONTROL SCHEME

Patent #:	8184635	Issue Dt:	05/22/2012	Application #:	12862497	Filing Dt:	08/24/2010
Publication #:	US20100325380	Pub Dt:	12/23/2010
Title:	PORT PACKET QUEUING

Patent #:	7957211	Issue Dt:	06/07/2011	Application #:	12878601	Filing Dt:	09/09/2010
Publication #:	US20100329051	Pub Dt:	12/30/2010
Title:	METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS

Patent #:	8904046	Issue Dt:	12/02/2014	Application #:	12879543	Filing Dt:	09/10/2010
Publication #:	US20100332685	Pub Dt:	12/30/2010
Title:	APPARATUS AND METHOD FOR CAPTURING SERIAL INPUT DATA

Patent #:	8289805	Issue Dt:	10/16/2012	Application #:	12879566	Filing Dt:	09/10/2010
Publication #:	US20110013455	Pub Dt:	01/20/2011
Title:	NON-VOLATILE MEMORY BANK AND PAGE BUFFER THEREFOR

Patent #:	8199598	Issue Dt:	06/12/2012	Application #:	12882931	Filing Dt:	09/15/2010
Publication #:	US20110002171	Pub Dt:	01/06/2011
Title:	MEMORY WITH OUTPUT CONTROL

Patent #:	8102708	Issue Dt:	01/24/2012	Application #:	12884939	Filing Dt:	09/17/2010
Publication #:	US20110007564	Pub Dt:	01/13/2011
Title:	FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME

Patent #:	7995401	Issue Dt:	08/09/2011	Application #:	12888034	Filing Dt:	09/22/2010
Publication #:	US20110069551	Pub Dt:	03/24/2011
Title:	NON-VOLATILE SEMICONDUCTOR MEMORY WITH PAGE ERASE

Patent #:	8195839	Issue Dt:	06/05/2012	Application #:	12892215	Filing Dt:	09/28/2010
Publication #:	US20110016236	Pub Dt:	01/20/2011
Title:	APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXED DEVICE TYPE IN A SERIAL INTERCONNECTION

Patent #:	8401013	Issue Dt:	03/19/2013	Application #:	12900395	Filing Dt:	10/07/2010
Publication #:	US20110019546	Pub Dt:	01/27/2011
Title:	CONGESTION MANAGEMENT IN A NETWORK

Patent #:	8064260	Issue Dt:	11/22/2011	Application #:	12903271	Filing Dt:	10/13/2010
Publication #:	US20110032773	Pub Dt:	02/10/2011
Title:	POWER SUPPLIES IN FLASH MEMORY DEVICES AND SYSTEMS

Patent #:	8429495	Issue Dt:	04/23/2013	Application #:	12907210	Filing Dt:	10/19/2010
Publication #:	US20120096330	Pub Dt:	04/19/2012
Title:	ERROR DETECTION AND CORRECTION CODES FOR CHANNELS AND MEMORIES WITH INCOMPLETE ERROR CHARACTERISTICS

Patent #:	8619538	Issue Dt:	12/31/2013	Application #:	12912235	Filing Dt:	10/26/2010
Publication #:	US20110038368	Pub Dt:	02/17/2011
Title:	COMMUNICATION SYSTEM AND METHOD OVER LOCAL AREA NETWORK WIRING

Patent #:	8035413	Issue Dt:	10/11/2011	Application #:	12915796	Filing Dt:	10/29/2010
Publication #:	US20110043246	Pub Dt:	02/24/2011
Title:	DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

Patent #:	8738203	Issue Dt:	05/27/2014	Application #:	12925403	Filing Dt:	10/19/2010
Publication #:	US20110112711	Pub Dt:	05/12/2011
Title:	METHOD, APPARATUS, SIGNALS, AND MEDIUM FOR MANAGING POWER IN A HYBRID VEHICLE

Patent #:	8443233	Issue Dt:	05/14/2013	Application #:	12945280	Filing Dt:	11/12/2010
Publication #:	US20110060937	Pub Dt:	03/10/2011
Title:	METHODS AND SYSTEMS FOR FAILURE ISOLATION AND DATA RECOVERY IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES

Patent #:	8713344	Issue Dt:	04/29/2014	Application #:	12948186	Filing Dt:	11/17/2010
Publication #:	US20110060934	Pub Dt:	03/10/2011
Title:	METHODS AND APPARATUS FOR CLOCK SIGNAL SYNCHRONIZATION IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES

Patent #:	8013646	Issue Dt:	09/06/2011	Application #:	12950305	Filing Dt:	11/19/2010
Publication #:	US20110063006	Pub Dt:	03/17/2011
Title:	TIMING VERNIER USING A DELAY LOCKED LOOP

Patent #:	8218386	Issue Dt:	07/10/2012	Application #:	12952560	Filing Dt:	11/23/2010
Publication #:	US20110211409	Pub Dt:	09/01/2011
Title:	EMBEDDED MEMORY DATABUS ARCHITECTURE

Patent #:	8421229	Issue Dt:	04/16/2013	Application #:	12958287	Filing Dt:	12/01/2010
Publication #:	US20110068474	Pub Dt:	03/24/2011
Title:	SEMICONDUCTOR DEVICE HAVING METAL LINES WITH SLITS

Patent #:	8966208	Issue Dt:	02/24/2015	Application #:	12967918	Filing Dt:	12/14/2010
Publication #:	US20110208906	Pub Dt:	08/25/2011
Title:	SEMICONDUCTOR MEMORY DEVICE WITH PLURAL MEMORY DIE AND CONTROLLER DIE

Patent #:	8296606	Issue Dt:	10/23/2012	Application #:	12982599	Filing Dt:	12/30/2010
Publication #:	US20110099417	Pub Dt:	04/28/2011
Title:	MEMORY DEVICE AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY

Patent #:	8379786	Issue Dt:	02/19/2013	Application #:	12984163	Filing Dt:	01/04/2011
Publication #:	US20110095796	Pub Dt:	04/28/2011
Title:	PROCESS, VOLTAGE, TEMPERATURE INDEPENDENT SWITCHED DELAY COMPENSATION SCHEME

Patent #:	8092258	Issue Dt:	01/10/2012	Application #:	12984834	Filing Dt:	01/05/2011
Publication #:	US20110097939	Pub Dt:	04/28/2011
Title:	MODULAR OUTLET

Patent #:	8406070	Issue Dt:	03/26/2013	Application #:	12984987	Filing Dt:	01/05/2011
Publication #:	US20110096614	Pub Dt:	04/28/2011
Title:	SINGLE-STROBE OPERATION OF MEMORY DEVICES

Patent #:	NONE	Issue Dt:		Application #:	12986539	Filing Dt:	01/07/2011
Publication #:	US20110096778	Pub Dt:	04/28/2011
Title:	OUTLET WITH ANALOG SIGNAL ADAPTER, A METHOD FOR USE THEREOF AND A NETWORK USING SAID OUTLET

Patent #:	8049541	Issue Dt:	11/01/2011	Application #:	12986646	Filing Dt:	01/07/2011
Publication #:	US20110102034	Pub Dt:	05/05/2011
Title:	CHARGE PUMP FOR PLL/DLL

Patent #:	8207769	Issue Dt:	06/26/2012	Application #:	12986684	Filing Dt:	01/07/2011
Publication #:	US20110109365	Pub Dt:	05/12/2011
Title:	DELAY LOCKED LOOP CIRCUIT

Patent #:	8374047	Issue Dt:	02/12/2013	Application #:	13004461	Filing Dt:	01/11/2011
Publication #:	US20110103169	Pub Dt:	05/05/2011
Title:	DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS

Patent #:	8211792	Issue Dt:	07/03/2012	Application #:	13005231	Filing Dt:	01/12/2011
Publication #:	US20110111589	Pub Dt:	05/12/2011
Title:	BARRIER-METAL-FREE COPPER CAMASCENCE TECHNOLOGY USING ATOMIC HYDROGEN ENHANCED REFLOW

Patent #:	8339826	Issue Dt:	12/25/2012	Application #:	13005774	Filing Dt:	01/13/2011
Publication #:	US20110110155	Pub Dt:	05/12/2011
Title:	STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE

Patent #:	8432767	Issue Dt:	04/30/2013	Application #:	13006005	Filing Dt:	01/13/2011
Publication #:	US20110110165	Pub Dt:	05/12/2011
Title:	CLOCK MODE DETERMINATION IN A MEMORY SYSTEM

Patent #:	8570828	Issue Dt:	10/29/2013	Application #:	13008522	Filing Dt:	01/18/2011
Publication #:	US20110252206	Pub Dt:	10/13/2011
Title:	MEMORY PROGRAMMING USING VARIABLE DATA WIDTH

Patent #:	8463959	Issue Dt:	06/11/2013	Application #:	13012754	Filing Dt:	01/24/2011
Publication #:	US20110296056	Pub Dt:	12/01/2011
Title:	HIGH-SPEED INTERFACE FOR DAISY-CHAINED DEVICES

Patent #:	NONE	Issue Dt:		Application #:	13016396	Filing Dt:	01/28/2011
Publication #:	US20110131383	Pub Dt:	06/02/2011
Title:	MODULAR COMMAND STRUCTURE FOR MEMORY AND MEMORY SYSTEM

Patent #:	8279685	Issue Dt:	10/02/2012	Application #:	13019100	Filing Dt:	02/01/2011
Publication #:	US20110122719	Pub Dt:	05/26/2011
Title:	PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES

Patent #:	8060691	Issue Dt:	11/15/2011	Application #:	13022166	Filing Dt:	02/07/2011
Publication #:	US20110131445	Pub Dt:	06/02/2011
Title:	APPARATUS AND METHOD OF PAGE PROGRAM OPERATION FOR MEMORY DEVICES WITH MIRROR BACK-UP OF DATA

Patent #:	NONE	Issue Dt:		Application #:	13023838	Filing Dt:	02/09/2011
Publication #:	US20110258366	Pub Dt:	10/20/2011
Title:	STATUS INDICATION IN A SYSTEM HAVING A PLURALITY OF MEMORY DEVICES

Patent #:	8081529	Issue Dt:	12/20/2011	Application #:	13030785	Filing Dt:	02/18/2011
Publication #:	US20110141835	Pub Dt:	06/16/2011
Title:	CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS

Patent #:	8149032	Issue Dt:	04/03/2012	Application #:	13032175	Filing Dt:	02/22/2011
Publication #:	US20110204939	Pub Dt:	08/25/2011
Title:	CIRCUIT FOR CLAMPING CURRENT IN A CHARGE PUMP

Patent #:	8392767	Issue Dt:	03/05/2013	Application #:	13033294	Filing Dt:	02/23/2011
Publication #:	US20110154137	Pub Dt:	06/23/2011
Title:	DATA CHANNEL TEST APPARATUS AND METHOD THEREOF

Patent #:	8145832	Issue Dt:	03/27/2012	Application #:	13035580	Filing Dt:	02/25/2011
Publication #:	US20110238894	Pub Dt:	09/29/2011
Title:	NON-VOLATILE MEMORY DEVICES AND CONTROL AND OPERATION THEREOF

Patent #:	NONE	Issue Dt:		Application #:	13037113	Filing Dt:	02/28/2011
Publication #:	US20110212628	Pub Dt:	09/01/2011
Title:	SEQUENTIAL PULSE DEPOSITION

Patent #:	9098430	Issue Dt:	08/04/2015	Application #:	13038461	Filing Dt:	03/02/2011
Publication #:	US20110231739	Pub Dt:	09/22/2011
Title:	COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION

Patent #:	8819377	Issue Dt:	08/26/2014	Application #:	13038997	Filing Dt:	03/02/2011
Publication #:	US20110153974	Pub Dt:	06/23/2011
Title:	SYSTEM AND METHOD OF OPERATING MEMORY DEVICES OF MIXED TYPE

Patent #:	8670262	Issue Dt:	03/11/2014	Application #:	13040254	Filing Dt:	03/03/2011
Publication #:	US20110153973	Pub Dt:	06/23/2011
Title:	HYBRID SOLID-STATE MEMORY SYSTEM HAVING VOLATILE AND NON-VOLATILE MEMORY

Patent #:	8462573	Issue Dt:	06/11/2013	Application #:	13040324	Filing Dt:	03/04/2011
Publication #:	US20110305098	Pub Dt:	12/15/2011
Title:	SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION

Patent #:	8502368	Issue Dt:	08/06/2013	Application #:	13042571	Filing Dt:	03/08/2011
Publication #:	US20120056335	Pub Dt:	03/08/2012
Title:	MULTI-CHIP PACKAGE WITH OFFSET DIE STACKING

Patent #:	NONE	Issue Dt:		Application #:	13044701	Filing Dt:	03/10/2011
Publication #:	US20110261613	Pub Dt:	10/27/2011
Title:	PHASE CHANGE MEMORY ARRAY BLOCKS WITH ALTERNATE SELECTION

Patent #:	8383514	Issue Dt:	02/26/2013	Application #:	13046197	Filing Dt:	03/11/2011
Publication #:	US20110163423	Pub Dt:	07/07/2011
Title:	METHOD FOR STACKING SERIALLY-CONNECTED INTEGRATED CIRCUITS AND MULTI-CHIP DEVICE MADE FROM SAME

Patent #:	8843692	Issue Dt:	09/23/2014	Application #:	13048154	Filing Dt:	03/15/2011
Publication #:	US20110264846	Pub Dt:	10/27/2011
Title:	SYSTEM OF INTERCONNECTED NONVOLATILE MEMORIES HAVING AUTOMATIC STATUS PACKET

Patent #:	8122218	Issue Dt:	02/21/2012	Application #:	13049487	Filing Dt:	03/16/2011
Publication #:	US20110202713	Pub Dt:	08/18/2011
Title:	SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE

100

Patent #:	8369170	Issue Dt:	02/05/2013	Application #:	13053727	Filing Dt:	03/22/2011
Publication #:	US20110170366	Pub Dt:	07/14/2011
Title:	TEMPERATURE DETECTOR IN AN INTEGRATED CIRCUIT

Assignor

MOSAID TECHNOLOGIES INCORPORATED

Exec Dt:

01/01/2014

Assignee

CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

11 HINES RD, SUITE 203

OTTAWA, ONTARIO, CANADA K2K2X1

Correspondence name and address
	CPA GLOBAL LIMITED
	LIBERATION HOUSE
	CASTLE STREET
	ST HELIER, JE1 1BL JERSEY

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