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Reel/Frame:032439/0638   Pages: 39
Recorded: 03/13/2014
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 1383
Page 14 of 14
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14
1
Patent #:
8891322
Issue Dt:
11/18/2014
Application #:
13621486
Filing Dt:
09/17/2012
Publication #:
US20130070547
Pub Dt:
03/21/2013
Title:
MEMORY SYSTEM WITH A LAYER COMPRISING A DEDICATED REDUNDANCY AREA
2
Patent #:
NONE
Issue Dt:
Application #:
13621887
Filing Dt:
09/18/2012
Publication #:
US20130068509
Pub Dt:
03/21/2013
Title:
METHOD AND APPARATUS FOR CONNECTING INLAID CHIP INTO PRINTED CIRCUIT BOARD
3
Patent #:
8533522
Issue Dt:
09/10/2013
Application #:
13624487
Filing Dt:
09/21/2012
Publication #:
US20130024717
Pub Dt:
01/24/2013
Title:
DOUBLE DATA RATE OUTPUT CIRCUIT
4
Patent #:
NONE
Issue Dt:
Application #:
13636547
Filing Dt:
09/21/2012
Publication #:
US20130033929
Pub Dt:
02/07/2013
Title:
WRITE SCHEME IN A PHASE CHANGE MEMORY
5
Patent #:
NONE
Issue Dt:
Application #:
13636574
Filing Dt:
09/21/2012
Publication #:
US20130016557
Pub Dt:
01/17/2013
Title:
SEMICONDUCTOR MEMORY DEVICE HAVING A THREE-DIMENSIONAL STRUCTURE
6
Patent #:
NONE
Issue Dt:
Application #:
13636585
Filing Dt:
09/21/2012
Publication #:
US20130021844
Pub Dt:
01/24/2013
Title:
PHASE CHANGE MEMORY WITH DOUBLE WRITE DRIVERS
7
Patent #:
9009423
Issue Dt:
04/14/2015
Application #:
13643317
Filing Dt:
11/06/2012
Publication #:
US20130086334
Pub Dt:
04/04/2013
Title:
SERIALLY CONNECTED MEMORY HAVING SUBDIVIDED DATA INTERFACE
8
Patent #:
8824231
Issue Dt:
09/02/2014
Application #:
13644528
Filing Dt:
10/04/2012
Publication #:
US20130083615
Pub Dt:
04/04/2013
Title:
REDUCED NOISE DRAM SENSING
9
Patent #:
8619473
Issue Dt:
12/31/2013
Application #:
13649403
Filing Dt:
10/11/2012
Publication #:
US20130033941
Pub Dt:
02/07/2013
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES
10
Patent #:
8743643
Issue Dt:
06/03/2014
Application #:
13650580
Filing Dt:
10/12/2012
Publication #:
US20130070539
Pub Dt:
03/21/2013
Title:
DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION
11
Patent #:
NONE
Issue Dt:
Application #:
13652947
Filing Dt:
10/16/2012
Publication #:
US20130343123
Pub Dt:
12/26/2013
Title:
FLASH MEMORY PROGRAM INHIBIT SCHEME
12
Patent #:
8677084
Issue Dt:
03/18/2014
Application #:
13655582
Filing Dt:
10/19/2012
Publication #:
US20130046921
Pub Dt:
02/21/2013
Title:
METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE
13
Patent #:
9159374
Issue Dt:
10/13/2015
Application #:
13665181
Filing Dt:
10/31/2012
Publication #:
US20130107443
Pub Dt:
05/02/2013
Title:
FLASH MEMORY MODULE AND MEMORY SUBSYSTEM
14
Patent #:
8694692
Issue Dt:
04/08/2014
Application #:
13671248
Filing Dt:
11/07/2012
Publication #:
US20130067118
Pub Dt:
03/14/2013
Title:
APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE
15
Patent #:
8655570
Issue Dt:
02/18/2014
Application #:
13674624
Filing Dt:
11/12/2012
Publication #:
US20130066503
Pub Dt:
03/14/2013
Title:
METHOD, APPARATUS, SIGNALS AND MEDIA, FOR SELECTING OPERATING CONDITIONS OF A GENSET
16
Patent #:
NONE
Issue Dt:
Application #:
13675163
Filing Dt:
11/13/2012
Publication #:
US20130119542
Pub Dt:
05/16/2013
Title:
PACKAGE HAVING STACKED MEMORY DIES WITH SERIALLY CONNECTED BUFFER DIES
17
Patent #:
NONE
Issue Dt:
Application #:
13676606
Filing Dt:
11/14/2012
Publication #:
US20130073754
Pub Dt:
03/21/2013
Title:
APPARATUS AND METHOD FOR ESTABLISHING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES
18
Patent #:
8879296
Issue Dt:
11/04/2014
Application #:
13684260
Filing Dt:
11/23/2012
Publication #:
US20130135917
Pub Dt:
05/30/2013
Title:
MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE
19
Patent #:
8836148
Issue Dt:
09/16/2014
Application #:
13687198
Filing Dt:
11/28/2012
Publication #:
US20130134607
Pub Dt:
05/30/2013
Title:
INTERPOSER FOR STACKED SEMICONDUCTOR DEVICES
20
Patent #:
9158344
Issue Dt:
10/13/2015
Application #:
13689070
Filing Dt:
11/29/2012
Publication #:
US20130141858
Pub Dt:
06/06/2013
Title:
CPU WITH STACKED MEMORY
21
Patent #:
8867523
Issue Dt:
10/21/2014
Application #:
13692305
Filing Dt:
12/03/2012
Publication #:
US20130215798
Pub Dt:
08/22/2013
Title:
LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
22
Patent #:
8593847
Issue Dt:
11/26/2013
Application #:
13713320
Filing Dt:
12/13/2012
Publication #:
US20130102111
Pub Dt:
04/25/2013
Title:
STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE
23
Patent #:
8704569
Issue Dt:
04/22/2014
Application #:
13718783
Filing Dt:
12/18/2012
Publication #:
US20130176061
Pub Dt:
07/11/2013
Title:
DELAY LOCKED LOOP CIRCUIT AND METHOD
24
Patent #:
9128662
Issue Dt:
09/08/2015
Application #:
13720951
Filing Dt:
12/19/2012
Publication #:
US20130163175
Pub Dt:
06/27/2013
Title:
SOLID STATE DRIVE MEMORY SYSTEM
25
Patent #:
8949945
Issue Dt:
02/03/2015
Application #:
13724022
Filing Dt:
12/21/2012
Publication #:
US20130117828
Pub Dt:
05/09/2013
Title:
DISTRIBUTED NETWORK MANAGEMENT HIERARCHY IN A MULTI-STATION COMMUNICATION NETWORK
26
Patent #:
NONE
Issue Dt:
Application #:
13726320
Filing Dt:
12/24/2012
Publication #:
US20130212304
Pub Dt:
08/15/2013
Title:
ASYNCHRONOUS ID GENERATION
27
Patent #:
8638638
Issue Dt:
01/28/2014
Application #:
13732791
Filing Dt:
01/02/2013
Publication #:
US20130121096
Pub Dt:
05/16/2013
Title:
DELAY LOCKED LOOP IMPLEMENTATION IN A SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
28
Patent #:
8897411
Issue Dt:
11/25/2014
Application #:
13741994
Filing Dt:
01/15/2013
Publication #:
US20130135019
Pub Dt:
05/30/2013
Title:
PROCESS, VOLTAGE, TEMPERATURE INDEPENDENT SWITCHED DELAY COMPENSATION SCHEME
29
Patent #:
8654573
Issue Dt:
02/18/2014
Application #:
13743794
Filing Dt:
01/17/2013
Publication #:
US20130132761
Pub Dt:
05/23/2013
Title:
HIGH BANDWIDTH MEMORY INTERFACE
30
Patent #:
8675408
Issue Dt:
03/18/2014
Application #:
13743899
Filing Dt:
01/17/2013
Publication #:
US20130128668
Pub Dt:
05/23/2013
Title:
NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE
31
Patent #:
9159647
Issue Dt:
10/13/2015
Application #:
13750046
Filing Dt:
01/25/2013
Publication #:
US20130193582
Pub Dt:
08/01/2013
Title:
METHOD AND APPARATUS FOR CONNECTING MEMORY DIES TO FORM A MEMORY SYSTEM
32
Patent #:
8855277
Issue Dt:
10/07/2014
Application #:
13751825
Filing Dt:
01/28/2013
Publication #:
US20130137296
Pub Dt:
05/30/2013
Title:
A TELEPHONE OUTLET FOR IMPLEMENTING A LOCAL AREA NETWORK OVER TELEPHONE LINES AND A LOCAL AREA NETWORK USING SUCH OUTLETS
33
Patent #:
8591264
Issue Dt:
11/26/2013
Application #:
13751865
Filing Dt:
01/28/2013
Publication #:
US20130210283
Pub Dt:
08/15/2013
Title:
MODULAR OUTLET
34
Patent #:
8885660
Issue Dt:
11/11/2014
Application #:
13754366
Filing Dt:
01/30/2013
Publication #:
US20130215799
Pub Dt:
08/22/2013
Title:
LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
35
Patent #:
8553457
Issue Dt:
10/08/2013
Application #:
13757250
Filing Dt:
02/01/2013
Publication #:
US20130141973
Pub Dt:
06/06/2013
Title:
NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION
36
Patent #:
8903581
Issue Dt:
12/02/2014
Application #:
13758019
Filing Dt:
02/04/2013
Publication #:
US20130143715
Pub Dt:
06/06/2013
Title:
METHOD AND APPARATUS FOR STARTING AN ENGINE IN A HYBRID VEHICLE
37
Patent #:
9183892
Issue Dt:
11/10/2015
Application #:
13765059
Filing Dt:
02/12/2013
Publication #:
US20130182485
Pub Dt:
07/18/2013
Title:
DATA STORAGE AND STACKABLE CHIP CONFIGURATIONS
38
Patent #:
8671252
Issue Dt:
03/11/2014
Application #:
13776757
Filing Dt:
02/26/2013
Publication #:
US20130170298
Pub Dt:
07/04/2013
Title:
SCALABLE MEMORY SYSTEM
39
Patent #:
8724384
Issue Dt:
05/13/2014
Application #:
13777485
Filing Dt:
02/26/2013
Publication #:
US20130170294
Pub Dt:
07/04/2013
Title:
MULTIPLE-BIT PER CELL (MBC) NON-VOLATILE MEMORY APPARATUS AND SYSTEM HAVING POLARITY CONTROL AND METHOD OF PROGRAMMING SAME
40
Patent #:
8711573
Issue Dt:
04/29/2014
Application #:
13777645
Filing Dt:
02/26/2013
Publication #:
US20130169343
Pub Dt:
07/04/2013
Title:
USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING
41
Patent #:
NONE
Issue Dt:
Application #:
13784361
Filing Dt:
03/04/2013
Publication #:
US20130176043
Pub Dt:
07/11/2013
Title:
DEVICE, METHOD AND SYSTEM FOR ESTIMATING THE TERMINATION TO A WIRED TRANSMISSION-LINE BASED ON DETERMINATION OF CHARACTERISTIC IMPEDANCE
42
Patent #:
9230654
Issue Dt:
01/05/2016
Application #:
13790361
Filing Dt:
03/08/2013
Publication #:
US20130188422
Pub Dt:
07/25/2013
Title:
METHOD AND SYSTEM FOR ACCESSING A FLASH MEMORY DEVICE
43
Patent #:
8855121
Issue Dt:
10/07/2014
Application #:
13795070
Filing Dt:
03/12/2013
Publication #:
US20130208596
Pub Dt:
08/15/2013
Title:
CONGESTION MANAGEMENT IN A NETWORK
44
Patent #:
9003214
Issue Dt:
04/07/2015
Application #:
13796677
Filing Dt:
03/12/2013
Publication #:
US20130275799
Pub Dt:
10/17/2013
Title:
CIRCUIT, SYSTEM AND METHOD FOR SELECTIVELY TURNING OFF INTERNAL CLOCK DRIVERS
45
Patent #:
NONE
Issue Dt:
Application #:
13799765
Filing Dt:
03/13/2013
Publication #:
US20130343125
Pub Dt:
12/26/2013
Title:
APPARATUS AND METHODS FOR CARRYING OUT OPERATIONS IN A NON-VOLATILE MEMORY CELL HAVING MULTIPLE MEMORY STATES
46
Patent #:
NONE
Issue Dt:
Application #:
13800897
Filing Dt:
03/13/2013
Publication #:
US20140036435
Pub Dt:
02/06/2014
Title:
STORAGE SYSTEM HAVING A HEATSINK
47
Patent #:
8946897
Issue Dt:
02/03/2015
Application #:
13826163
Filing Dt:
03/14/2013
Publication #:
US20130193583
Pub Dt:
08/01/2013
Title:
SEMICONDUCTOR DEVICE HAVING METAL LINES WITH SLITS
48
Patent #:
NONE
Issue Dt:
Application #:
13834009
Filing Dt:
03/15/2013
Publication #:
US20140016389
Pub Dt:
01/16/2014
Title:
DRAM MEMORY CELLS RECONFIGURED TO PROVIDE BULK CAPACITANCE
49
Patent #:
8675425
Issue Dt:
03/18/2014
Application #:
13836702
Filing Dt:
03/15/2013
Publication #:
US20130201775
Pub Dt:
08/08/2013
Title:
SINGLE-STROBE OPERATION OF MEMORY DEVICES
50
Patent #:
8599984
Issue Dt:
12/03/2013
Application #:
13850500
Filing Dt:
03/26/2013
Publication #:
US20130271192
Pub Dt:
10/17/2013
Title:
WIDE FREQUENCY RANGE DELAY LOCKED LOOP
51
Patent #:
8780622
Issue Dt:
07/15/2014
Application #:
13860724
Filing Dt:
04/11/2013
Publication #:
US20130215677
Pub Dt:
08/22/2013
Title:
PHASE-CHANGE MEMORY WITH MULTIPLE POLARITY BITS HAVING ENHANCED ENDURANCE AND ERROR TOLERANCE
52
Patent #:
8806305
Issue Dt:
08/12/2014
Application #:
13865514
Filing Dt:
04/18/2013
Publication #:
US20130232393
Pub Dt:
09/05/2013
Title:
ERROR DETECTION AND CORRECTION CODES FOR CHANNELS AND MEMORIES WITH INCOMPLETE ERROR CHARACTERISTICS
53
Patent #:
NONE
Issue Dt:
Application #:
13867158
Filing Dt:
04/22/2013
Publication #:
US20130237182
Pub Dt:
09/12/2013
Title:
MULTI-HAZARD ALARM SYSTEM USING SELECTABLE POWER-LEVEL TRANSMISSION AND LOCALIZATION
54
Patent #:
8654601
Issue Dt:
02/18/2014
Application #:
13867437
Filing Dt:
04/22/2013
Publication #:
US20130229874
Pub Dt:
09/05/2013
Title:
MEMORY WITH OUTPUT CONTROL
55
Patent #:
8644108
Issue Dt:
02/04/2014
Application #:
13871487
Filing Dt:
04/26/2013
Publication #:
US20130235659
Pub Dt:
09/12/2013
Title:
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
56
Patent #:
8860480
Issue Dt:
10/14/2014
Application #:
13873503
Filing Dt:
04/30/2013
Publication #:
US20130234787
Pub Dt:
09/12/2013
Title:
CIRCUIT FOR CLAMPING CURRENT IN A CHARGE PUMP
57
Patent #:
8837655
Issue Dt:
09/16/2014
Application #:
13887937
Filing Dt:
05/06/2013
Publication #:
US20130243137
Pub Dt:
09/19/2013
Title:
MEMORY CONTROLLER WITH FLEXIBLE DATA ALIGNMENT TO CLOCK
58
Patent #:
8711621
Issue Dt:
04/29/2014
Application #:
13892743
Filing Dt:
05/13/2013
Publication #:
US20130242653
Pub Dt:
09/19/2013
Title:
FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME
59
Patent #:
9214233
Issue Dt:
12/15/2015
Application #:
13895591
Filing Dt:
05/16/2013
Publication #:
US20130250695
Pub Dt:
09/26/2013
Title:
METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE
60
Patent #:
8839754
Issue Dt:
09/23/2014
Application #:
13902088
Filing Dt:
05/24/2013
Publication #:
US20130332055
Pub Dt:
12/12/2013
Title:
METHOD AND APPARATUS FOR STARTING AN INTERNAL COMBUSTION ENGINE
61
Patent #:
NONE
Issue Dt:
Application #:
13903319
Filing Dt:
05/28/2013
Publication #:
US20130249592
Pub Dt:
09/26/2013
Title:
TERMINATION CIRCUIT FOR ON-DIE TERMINATION
62
Patent #:
NONE
Issue Dt:
Application #:
13903418
Filing Dt:
05/28/2013
Publication #:
US20130326090
Pub Dt:
12/05/2013
Title:
RING TOPOLOGY STATUS INDICATION
63
Patent #:
8780664
Issue Dt:
07/15/2014
Application #:
13912650
Filing Dt:
06/07/2013
Publication #:
US20130265839
Pub Dt:
10/10/2013
Title:
SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION
64
Patent #:
NONE
Issue Dt:
Application #:
13914126
Filing Dt:
06/10/2013
Publication #:
US20130275628
Pub Dt:
10/17/2013
Title:
HIGH SPEED INTERFACE FOR DAISY-CHAINED DEVICES
65
Patent #:
8908378
Issue Dt:
12/09/2014
Application #:
13917728
Filing Dt:
06/14/2013
Publication #:
US20130271910
Pub Dt:
10/17/2013
Title:
SYSTEM INCLUDING A PLURALITY OF ENCAPSULATED SEMICONDUCTOR CHIPS
66
Patent #:
9177863
Issue Dt:
11/03/2015
Application #:
13951132
Filing Dt:
07/25/2013
Publication #:
US20130309810
Pub Dt:
11/21/2013
Title:
MULTI-CHIP PACKAGE WITH OFFSET DIE STACKING AND METHOD OF MAKING SAME
67
Patent #:
NONE
Issue Dt:
Application #:
13955809
Filing Dt:
07/31/2013
Publication #:
US20130318287
Pub Dt:
11/28/2013
Title:
BRIDGING DEVICE HAVING A FREQUENCY CONFIGURABLE CLOCK DOMAIN
68
Patent #:
8817779
Issue Dt:
08/26/2014
Application #:
13956933
Filing Dt:
08/01/2013
Publication #:
US20130315048
Pub Dt:
11/28/2013
Title:
TELEPHONE COMMUNICATION SYSTEM AND METHOD OVER LOCAL AREA NETWORK WIRING
69
Patent #:
8767430
Issue Dt:
07/01/2014
Application #:
13957713
Filing Dt:
08/02/2013
Publication #:
US20130322173
Pub Dt:
12/05/2013
Title:
CONFIGURABLE MODULE AND MEMORY SUBSYSTEM
70
Patent #:
8898415
Issue Dt:
11/25/2014
Application #:
13962062
Filing Dt:
08/08/2013
Publication #:
US20140013041
Pub Dt:
01/09/2014
Title:
SIMULTANEOUS READ AND WRITE DATA TRANSFER
71
Patent #:
NONE
Issue Dt:
Application #:
13966891
Filing Dt:
08/14/2013
Publication #:
US20130329482
Pub Dt:
12/12/2013
Title:
HIGH BANDWIDTH MEMORY INTERFACE
72
Patent #:
NONE
Issue Dt:
Application #:
13969184
Filing Dt:
08/16/2013
Publication #:
US20130336063
Pub Dt:
12/19/2013
Title:
Non-Volatile Semiconductor Memory with Page Erase
73
Patent #:
NONE
Issue Dt:
Application #:
13973574
Filing Dt:
08/22/2013
Publication #:
US20130343142
Pub Dt:
12/26/2013
Title:
DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR
74
Patent #:
8879311
Issue Dt:
11/04/2014
Application #:
13973600
Filing Dt:
08/22/2013
Publication #:
US20130336055
Pub Dt:
12/19/2013
Title:
PHASE CHANGE MEMORY WORD LINE DRIVER
75
Patent #:
8767461
Issue Dt:
07/01/2014
Application #:
14022805
Filing Dt:
09/10/2013
Publication #:
US20140010019
Pub Dt:
01/09/2014
Title:
NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION
76
Patent #:
8754687
Issue Dt:
06/17/2014
Application #:
14023047
Filing Dt:
09/10/2013
Publication #:
US20140009196
Pub Dt:
01/09/2014
Title:
FREQUENCY-DOUBLING DELAY LOCKED LOOP
77
Patent #:
8837237
Issue Dt:
09/16/2014
Application #:
14026359
Filing Dt:
09/13/2013
Publication #:
US20140010022
Pub Dt:
01/09/2014
Title:
DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE
78
Patent #:
9977731
Issue Dt:
05/22/2018
Application #:
14027858
Filing Dt:
09/16/2013
Publication #:
US20140019705
Pub Dt:
01/16/2014
Title:
BRIDGING DEVICE HAVING A CONFIGURABLE VIRTUAL PAGE SIZE
79
Patent #:
NONE
Issue Dt:
Application #:
14030194
Filing Dt:
09/18/2013
Publication #:
US20140016652
Pub Dt:
01/16/2014
Title:
DYNAMIC TRAFFIC REARRANGEMENT AND RESTORATION FOR MPLS NETWORKS WITH DIFFERENTIATED SERVICES CAPABILITIES
80
Patent #:
9070461
Issue Dt:
06/30/2015
Application #:
14032816
Filing Dt:
09/20/2013
Publication #:
US20140022846
Pub Dt:
01/23/2014
Title:
NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES
81
Patent #:
8897090
Issue Dt:
11/25/2014
Application #:
14045857
Filing Dt:
10/04/2013
Publication #:
US20140029347
Pub Dt:
01/30/2014
Title:
MEMORY SYSTEM HAVING A PLURALITY OF SERIALLY CONNECTED DEVICES
82
Patent #:
NONE
Issue Dt:
Application #:
14053828
Filing Dt:
10/15/2013
Publication #:
US20140035615
Pub Dt:
02/06/2014
Title:
SYSTEM FOR TRANSMISSION LINE TERMINATION BY SIGNAL CANCELLATION
83
Patent #:
NONE
Issue Dt:
Application #:
14064442
Filing Dt:
10/28/2013
Publication #:
US20140050228
Pub Dt:
02/20/2014
Title:
LOCAL AREA NETWORK FOR DISTRIBUTING DATA COMMUNICATION, SENSING AND CONTROL SIGNALS
Assignor
1
MOSAID TECHNOLOGIES INCORPORATED
Exec Dt:
01/01/2014
Assignee
1
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
11 HINES RD, SUITE 203
OTTAWA, ONTARIO, CANADA K2K2X1
Correspondence name and address
CPA GLOBAL LIMITED
LIBERATION HOUSE
CASTLE STREET
ST HELIER, JE1 1BL JERSEY

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