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VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY
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Patent #:
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Issue Dt:
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03/14/2006
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Application #:
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11203046
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Filing Dt:
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08/12/2005
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Publication #:
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Pub Dt:
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01/05/2006
| | | | |
Title:
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SEMICONDUCTOR CONSTRUCTIONS
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Patent #:
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Issue Dt:
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10/31/2006
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Application #:
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11205082
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Filing Dt:
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08/17/2005
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Publication #:
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Pub Dt:
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01/26/2006
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Title:
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TIMING VERNIER USING A DELAY LOCKED LOOP
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Patent #:
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Issue Dt:
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12/26/2006
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Application #:
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11206529
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Filing Dt:
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08/18/2005
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Publication #:
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Pub Dt:
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12/15/2005
| | | | |
Title:
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CONTIGUOUS BLOCK ADDRESSING SCHEME
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Patent #:
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Issue Dt:
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12/26/2006
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Application #:
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11207017
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Filing Dt:
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08/18/2005
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Publication #:
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Pub Dt:
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12/15/2005
| | | | |
Title:
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CONTIGUOUS BLOCK ADDRESSING SCHEME
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Patent #:
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Issue Dt:
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12/26/2006
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Application #:
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11207105
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Filing Dt:
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08/18/2005
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Publication #:
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Pub Dt:
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12/15/2005
| | | | |
Title:
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CONTIGUOUS BLOCK ADDRESSING SCHEME
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Patent #:
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Issue Dt:
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05/22/2007
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Application #:
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11234302
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Filing Dt:
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09/26/2005
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Publication #:
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Pub Dt:
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01/26/2006
| | | | |
Title:
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LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
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Patent #:
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Issue Dt:
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03/06/2007
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Application #:
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11234314
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Filing Dt:
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09/26/2005
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Publication #:
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Pub Dt:
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01/26/2006
| | | | |
Title:
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LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
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Patent #:
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Issue Dt:
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10/13/2009
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Application #:
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11238973
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Filing Dt:
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09/30/2005
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Publication #:
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Pub Dt:
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04/05/2007
| | | | |
Title:
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POWER UP CIRCUIT WITH LOW POWER SLEEP MODE OPERATION
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Patent #:
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Issue Dt:
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11/06/2007
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Application #:
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11238975
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Filing Dt:
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09/30/2005
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Publication #:
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Pub Dt:
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04/05/2007
| | | | |
Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT HAVING CURRENT LEAKAGE REDUCTION SCHEME
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Patent #:
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Issue Dt:
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11/03/2009
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Application #:
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11239759
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Filing Dt:
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09/30/2005
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Title:
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METHOD AND APPARATUS FOR INTRODUCING A DELAY DURING A CALL SETUP IN A COMMUNICATION NETWORK
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Patent #:
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Issue Dt:
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12/08/2009
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Application #:
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11257525
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Filing Dt:
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10/25/2005
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Publication #:
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Pub Dt:
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03/23/2006
| | | | |
Title:
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METHOD AND SYSTEM FOR PACKET ENCRYPTION
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Patent #:
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Issue Dt:
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05/06/2008
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Application #:
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11261493
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Filing Dt:
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10/31/2005
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Publication #:
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Pub Dt:
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05/03/2007
| | | | |
Title:
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DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS
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Patent #:
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Issue Dt:
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10/17/2006
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Application #:
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11263144
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Filing Dt:
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10/31/2005
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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SORTING METHOD AND APPARATUS USING A CAM
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Patent #:
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Issue Dt:
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11/09/2010
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Application #:
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11264011
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Filing Dt:
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11/02/2005
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Publication #:
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Pub Dt:
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03/16/2006
| | | | |
Title:
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LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
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Patent #:
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Issue Dt:
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07/06/2010
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Application #:
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11264283
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Filing Dt:
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10/31/2005
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
Title:
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PHASE-LOCKED LOOP CIRCUITRY USING CHARGE PUMPS WITH CURRENT MIRROR CIRCUITRY
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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11268760
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Filing Dt:
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11/08/2005
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Publication #:
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Pub Dt:
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05/25/2006
| | | | |
Title:
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SYNCHRONOUS DRAM WITH SELECTABLE INTERNAL PREFETCH SIZE
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Patent #:
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Issue Dt:
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07/31/2007
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Application #:
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11269659
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Filing Dt:
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11/09/2005
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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MATCHLINE SENSE CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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06/21/2011
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Application #:
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11272775
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Filing Dt:
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11/15/2005
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Publication #:
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Pub Dt:
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03/23/2006
| | | | |
Title:
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LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
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Patent #:
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Issue Dt:
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12/04/2012
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Application #:
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11274276
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Filing Dt:
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11/16/2005
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Publication #:
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Pub Dt:
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04/13/2006
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Title:
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LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
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Patent #:
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Issue Dt:
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04/20/2010
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Application #:
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11287335
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Filing Dt:
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11/28/2005
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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METHOD AND SYSTEM FOR PROVIDING DC POWER ON LOCAL TELEPHONE LINES
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Patent #:
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Issue Dt:
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06/10/2008
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Application #:
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11289428
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Filing Dt:
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11/30/2005
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Publication #:
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Pub Dt:
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05/31/2007
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT HAVING LOW POWER CONSUMPTION WITH SELF-REFRESH
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Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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11295492
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Filing Dt:
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12/07/2005
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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11298978
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Filing Dt:
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12/09/2005
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Publication #:
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Pub Dt:
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06/22/2006
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Title:
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CHEMICAL VAPOR DEPOSITION OF TITANIUM FROM TITANIUM TETRACHLORIDE AND HYDROCARBON REACTANTS
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Patent #:
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Issue Dt:
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11/11/2014
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Application #:
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11300313
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Filing Dt:
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12/15/2005
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Publication #:
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Pub Dt:
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05/04/2006
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Title:
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LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
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Patent #:
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Issue Dt:
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09/29/2009
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11305433
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12/14/2005
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Pub Dt:
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05/18/2006
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Title:
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SYNCHRONIZATION CIRCUIT AND METHOD WITH TRANSPARENT LATCHES
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Patent #:
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Issue Dt:
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11/18/2008
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11312472
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12/21/2005
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Pub Dt:
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05/11/2006
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Title:
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OUTLET WITH ANALOG SIGNAL ADAPTER, A METHOD FOR USE THEREOF AND A NETWORK USING SAID OUTLET
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Issue Dt:
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04/22/2008
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11319451
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Filing Dt:
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12/29/2005
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Publication #:
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Pub Dt:
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07/26/2007
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Title:
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APPARATUS AND METHOD FOR SELF-REFRESHING DYNAMIC RANDOM ACCESS MEMORY CELLS
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Patent #:
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Issue Dt:
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06/05/2007
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11320746
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Filing Dt:
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12/30/2005
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Pub Dt:
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05/18/2006
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Title:
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MISMATCH-DEPENDENT POWER ALLOCATION TECHNIQUE FOR MATCH-LINE SENSING IN CONTENT-ADDRESSABLE MEMORIES
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Issue Dt:
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07/20/2010
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11322160
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12/29/2005
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07/05/2007
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Title:
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ASIC DESIGN USING CLOCK AND POWER GRID STANDARD CELL
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07/22/2008
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11323814
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12/29/2005
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11/16/2006
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Title:
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METHOD AND APPARATUS FOR REDUCING POOL STARVATION IN A SHARED MEMORY SWITCH
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01/26/2010
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11324023
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12/30/2005
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04/05/2007
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Title:
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MULTIPLE INDEPENDENT SERIAL LINK MEMORY
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01/01/2008
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11333629
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12/29/2005
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06/15/2006
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Title:
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CHEMICAL TREATMENT OF SEMICONDUCTOR SUBSTRATES
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08/19/2008
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11336097
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01/20/2006
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06/08/2006
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POWER MANAGERS FOR AN INTEGRATED CIRCUIT
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04/21/2009
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11338855
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01/25/2006
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06/22/2006
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TELEPHONE OUTLET FOR IMPLEMENTING A LOCAL AREA NETWORK OVER TELEPHONE LINES AND A LOCAL AREA NETWORK USING SUCH OUTLETS
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11/06/2007
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11339624
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01/26/2006
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07/06/2006
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Title:
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INTERNAL POWER MANAGEMENT SCHEME FOR A MEMORY CHIP IN DEEP POWER DOWN MODE
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02/26/2008
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11346396
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02/03/2006
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06/15/2006
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Title:
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SYSTEM FOR TRANSMISSION LINE TERMINATION BY SIGNAL CANCELLATION
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12/25/2007
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11347289
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02/06/2006
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08/09/2007
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Title:
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VOLTAGE LEVEL SHIFTER CIRCUIT
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02/26/2008
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11358767
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02/21/2006
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08/23/2007
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Title:
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NON-VOLATILE MEMORY DEVICE WITH PAGE BUFFER HAVING DUAL REGISTERS AND METHODS USING THE SAME
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06/30/2009
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11363251
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02/28/2006
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08/30/2007
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Title:
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LOW POWER MEMORY ARCHITECTURE
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01/30/2007
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11367467
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03/03/2006
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07/20/2006
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DATA PATH HAVING GROUNDED PRECHARGE OPERATION AND TEST COMPRESSION CAPABILITY
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11/11/2008
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11367589
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03/06/2006
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07/06/2006
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Title:
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HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY
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