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Patent Assignment Details
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Reel/Frame:026795/0644   Pages: 8
Recorded: 08/23/2011
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE PREVIOUSLY RECORDED ON REEL 021731 FRAME 0700. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT ASSIGNEES ARE SUN MICROSYSTEMS, INC. AND SUN MICROSYSTEMS TECHNOLOGY LTD.
Total properties: 28
1
Patent #:
Issue Dt:
04/01/2003
Application #:
09566901
Filing Dt:
05/10/2000
Title:
SOFTWARE CONTROL OF DRAM REFRESH TO REDUCE POWER CONSUMPTION IN A DATA PROCESSING SYSTEM
2
Patent #:
Issue Dt:
02/19/2002
Application #:
09609490
Filing Dt:
07/05/2000
Title:
Dynamic programmable logic array that can be reprogrammed and a method of use
3
Patent #:
Issue Dt:
08/13/2002
Application #:
09640486
Filing Dt:
08/16/2000
Title:
CONFIGURABLE DYNAMIC PROGRAMMABLE LOGIC ARRAY
4
Patent #:
Issue Dt:
10/16/2001
Application #:
09661137
Filing Dt:
09/13/2000
Title:
Repairable dynamic programmable logic array
5
Patent #:
Issue Dt:
12/31/2002
Application #:
09680672
Filing Dt:
10/06/2000
Title:
SELF-ADJUSTING MULTI-SPEED PIPELINE
6
Patent #:
Issue Dt:
10/18/2005
Application #:
10004338
Filing Dt:
11/14/2001
Publication #:
Pub Dt:
05/15/2003
Title:
OPERAND FILE USING POINTERS AND REFERENCE COUNTERS AND A METHOD OF USE
7
Patent #:
Issue Dt:
01/25/2005
Application #:
10045127
Filing Dt:
10/26/2001
Publication #:
Pub Dt:
05/01/2003
Title:
METHOD AND SYSTEM FOR PROGRAMMABLE REPLACEMENT MECHANISM FOR CACHING DEVICES
8
Patent #:
Issue Dt:
05/17/2005
Application #:
10054471
Filing Dt:
01/18/2002
Publication #:
Pub Dt:
05/30/2002
Title:
DYNAMIC PROGRAMMABLE LOGIC ARRAY THAT CAN BE REPROGRAMMED AND A METHOD OF USE
9
Patent #:
Issue Dt:
09/02/2003
Application #:
10071966
Filing Dt:
02/05/2002
Publication #:
Pub Dt:
08/29/2002
Title:
FIELD-PROGRAMMABLE DYNAMIC LOGIC ARRAY
10
Patent #:
Issue Dt:
06/17/2008
Application #:
11277761
Filing Dt:
03/29/2006
Title:
ADAPTIVE COMPUTING ENSEMBLE MICROPROCESSOR ARCHITECTURE
11
Patent #:
Issue Dt:
05/12/2009
Application #:
11279880
Filing Dt:
04/15/2006
Title:
IMPROVED PREFETCH HARDWARE EFFICIENCY VIA PREFETCH HINT INSTRUCTIONS
12
Patent #:
Issue Dt:
03/02/2010
Application #:
11306000
Filing Dt:
12/16/2005
Title:
SOFTWARE HINT TO SPECIFY THE PREFERRED BRANCH PREDICTION TO USE FOR A BRANCH INSTRUCTION
13
Patent #:
NONE
Issue Dt:
Application #:
11525971
Filing Dt:
09/25/2006
Publication #:
Pub Dt:
03/29/2007
Title:
METHOD OF TESTING A SUBSTRATE USING MULTRIPLE IMAGE-OBTAINING UNITS AND APPARATUS FOR PERFORMING THE SAME
14
Patent #:
Issue Dt:
09/18/2012
Application #:
11525972
Filing Dt:
09/25/2006
Publication #:
Pub Dt:
03/29/2007
Title:
PLUNGER DRIVING STRUCTURE
15
Patent #:
Issue Dt:
10/20/2009
Application #:
11535977
Filing Dt:
09/27/2006
Title:
TRACE CACHE FOR EFFICIENT SELF-MODIFYING CODE PROCESSING
16
Patent #:
Issue Dt:
09/08/2009
Application #:
11553453
Filing Dt:
10/26/2006
Title:
FLAG MANAGEMENT IN PROCESSORS ENABLED FOR SPECULATIVE EXECUTION OF MICRO-OPERATION TRACES
17
Patent #:
Issue Dt:
07/28/2009
Application #:
11553455
Filing Dt:
10/26/2006
Title:
FLAG MANAGEMENT IN PROCESSORS ENABLED FOR SPECULATIVE EXECUTION OF MICRO-OPERATION TRACES
18
Patent #:
Issue Dt:
07/28/2009
Application #:
11553458
Filing Dt:
10/26/2006
Title:
FLAG MANAGEMENT IN PROCESSORS ENABLED FOR SPECULATIVE EXECUTION OF MICRO-OPERATION TRACES
19
Patent #:
Issue Dt:
09/14/2010
Application #:
11561274
Filing Dt:
11/17/2006
Title:
TRACE OPTIMIZATION VIA FUSING OPERATIONS OF A TARGET ARCHITECTURE OPERATION SET
20
Patent #:
Issue Dt:
03/16/2010
Application #:
11561287
Filing Dt:
11/17/2006
Title:
EXECUTING FUNCTIONS DETERMINED VIA A COLLECTION OF OPERATIONS FROM TRANSLATED INSTRUCTIONS
21
Patent #:
Issue Dt:
06/17/2008
Application #:
11566206
Filing Dt:
12/01/2006
Title:
MICROARCHITECTURE FOR COMPACT STORAGE OF EMBEDDED CONSTANTS
22
Patent #:
Issue Dt:
12/21/2010
Application #:
11645901
Filing Dt:
12/26/2006
Title:
PREDICTION OF DATA VALUES READ FROM MEMORY BY A MICROPROCESSOR USING A DYNAMIC CONFIDENCE THRESHOLD
23
Patent #:
Issue Dt:
10/28/2008
Application #:
11740892
Filing Dt:
04/26/2007
Title:
REDUCED-POWER MEMORY WITH PER-SECTOR GROUND CONTROL
24
Patent #:
Issue Dt:
02/16/2010
Application #:
11740901
Filing Dt:
04/26/2007
Title:
REDUCED-POWER MEMORY WITH PER-SECTOR POWER/GROUND CONTROL AND EARLY ADDRESS
25
Patent #:
Issue Dt:
01/12/2010
Application #:
11751949
Filing Dt:
05/22/2007
Title:
RE-FETCHING CACHE MEMORY ENABLING LOW-POWER MODES
26
Patent #:
Issue Dt:
04/26/2011
Application #:
11751973
Filing Dt:
05/22/2007
Title:
RE-FETCHING CACHE MEMORY ENABLING ALTERNATIVE OPERATIONAL MODES
27
Patent #:
Issue Dt:
01/18/2011
Application #:
11751985
Filing Dt:
05/22/2007
Title:
RE-FETCHING CACHE MEMORY HAVING COHERENT RE-FETCHING
28
Patent #:
Issue Dt:
06/25/2013
Application #:
11774583
Filing Dt:
07/07/2007
Title:
CONTROLLING OPERATION OF A PROCESSOR ACCORDING TO EXECUTION MODE OF AN INSTRUCTION SEQUENCE
Assignor
1
Exec Dt:
04/17/2008
Assignees
1
4150 NETWORK CIRCLE
SANTA CLARA, CALIFORNIA 95054
2
CEDAR HOUSE, 41 CEDAR AVENUE
HAMILTON, BERMUDA HM12
Correspondence name and address
OSHA LIANG LLP
909 FANNIN STREET, SUITE 3500
HOUSTON, TX 77010

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