Total properties:
35
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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08978107
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Filing Dt:
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11/25/1997
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Title:
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METHOD OF FABRICATING A HIGH DIELECTRIC CONSTANT INTERPOLYSILICON DIELECTRIC STRUCTURE FOR A LOW VOLTAGE NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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08978398
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Filing Dt:
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11/25/1997
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Title:
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METHOD OF FABRICATING AN OXYNITRIDE-CAPPED HIGH DIELECTRIC CONSTANT INTERPOLYSILICON DIELECTRIC STRUCTURE FOR A LOW VOLTAGE NON-VOLATILE MEMORY.
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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08992961
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Filing Dt:
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12/18/1997
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Title:
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NON-VOLATILE TRENCH SEMICONDUCTOR DEVICE HAVING A SHALLOW DRAIN REGION
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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08993149
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Filing Dt:
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12/18/1997
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Title:
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METHODOLOGY FOR ACHIEVING DUAL FIELD OXIDE THICKNESSES
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Patent #:
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Issue Dt:
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06/27/2000
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Application #:
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08993716
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Filing Dt:
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12/18/1997
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Title:
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METHODOLOGY FOR ACHIEVING DUAL GATE OXIDE THICKNESSES
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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08993890
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Filing Dt:
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12/18/1997
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Title:
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NON- VOLATILE TRENCH SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09006495
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Filing Dt:
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01/13/1998
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Title:
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TRUNGSTEN PLUG FORMATION
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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09008415
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Filing Dt:
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01/16/1998
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Title:
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PROCESS FOR FABRICATING A FLASH MEMORY WITH DUAL FUNCTION CONTROL LINES
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09032362
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Filing Dt:
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02/27/1998
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Title:
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MULTIPLE CHIP HYBRID PACKAGE USING BUMP TECHNOLOGY
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09032398
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Filing Dt:
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02/27/1998
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Title:
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MULTI-CHIP PACKAGING USING BUMP TECHNOLOGY
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09033723
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Filing Dt:
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03/03/1998
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Title:
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ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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09033836
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Filing Dt:
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03/03/1998
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Title:
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ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRI NGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
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Patent #:
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Issue Dt:
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02/29/2000
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Application #:
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09033916
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Filing Dt:
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03/03/1998
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Title:
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ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09039783
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Filing Dt:
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03/16/1998
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Title:
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LARGE ANGLE IMPLANTATION TO PREVENT FIELD TURN-ON UNDER SELECT GATE TRANSISTOR FIELD OXIDE REGION FOR NON-VOLATILE MEMORY DEVICES
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Patent #:
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Issue Dt:
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11/23/1999
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Application #:
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09052062
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Filing Dt:
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03/30/1998
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Title:
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TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD WITH CORNER DOPING AND SIDEWALL DOPING
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Patent #:
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Issue Dt:
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11/21/2000
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Application #:
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09099057
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Filing Dt:
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06/17/1998
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Title:
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METHOD FOR SIMULTANEOUS DEPOSITION AND SPUTTERING OF TEOS
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|
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Patent #:
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|
Issue Dt:
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07/27/1999
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Application #:
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09103041
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Filing Dt:
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06/23/1998
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Title:
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PAGE BUFFER FOR A MULTI-LEVEL FLASH MEMORY WITH A LIMITED NUMBER OF LATCHES PER MEMORY CELL
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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09103046
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Filing Dt:
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06/23/1998
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Title:
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INTERLACED STORAGE AND SENSE TECHNIQUE FOR FLASH MULTI-LEVEL DEVICES
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09106177
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Filing Dt:
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06/29/1998
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Title:
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EEPROM HAVING STACKED DIELECTRIC TO INCREASE PROGRAMMING SPEED
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09108529
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Filing Dt:
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07/01/1998
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Title:
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PROGRAM/VERIFY TECHNIQUE FOR MULTI-LEVEL FLASH CELLS ENABLING DIFFERENT THRESHOLD LEVELS TO BE SIMULTANEOUSLY PROGRAMMED
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09110446
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Filing Dt:
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07/07/1998
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Title:
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DOUBLE DENSITY NON-VOLATILE MEMEORY CELLS
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09146032
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Filing Dt:
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09/02/1998
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Title:
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METHOD FOR MANUFACTURING MEMORY DEVICES
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09182525
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Filing Dt:
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10/30/1998
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Title:
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HIGH VOLTAGE TRANSISTOR WITH LOW BODY EFFECT AND LOW LEAKAGE
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09252185
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Filing Dt:
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02/18/1999
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Title:
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LOW DIELECTRIC SEMICONDUCTOR DEVICE WITH RIGID, CONDUCTIVELY LINED INTERCONNECTION SYSTEM
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Patent #:
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|
Issue Dt:
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06/24/2003
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Application #:
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09314574
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Filing Dt:
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05/18/1999
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Title:
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DATA PRE-READING AND ERROR CORRECTION CIRCUIT FOR A MEMORY DEVICE
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Patent #:
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|
Issue Dt:
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08/20/2002
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Application #:
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09314575
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Filing Dt:
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05/18/1999
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Title:
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METHOD OF DUAL USE OF NON-VOLATILE MEMORY FOR ERROR CORRECTION
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Patent #:
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Issue Dt:
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01/16/2001
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Application #:
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09408846
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Filing Dt:
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09/30/1999
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Title:
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READ OPERATION SCHEME FOR A HIGH-DENSITY, LOW VOLTAGE, AND SUPERIOR RELIABILITY NAND FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09436503
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Filing Dt:
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11/09/1999
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Title:
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DOUBLE DENSITY NON-VOLATILE MEMORY CELLS
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|
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Patent #:
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|
Issue Dt:
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09/24/2002
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Application #:
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09506298
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Filing Dt:
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02/17/2000
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Title:
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ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
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Patent #:
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|
Issue Dt:
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05/15/2001
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Application #:
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09562442
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Filing Dt:
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05/01/2000
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Title:
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Methodology for achieving dual gate oxide thicknesses
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Patent #:
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|
Issue Dt:
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03/30/2004
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Application #:
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09639798
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Filing Dt:
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08/17/2000
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Title:
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MASK FOR AND METHOD OF FORMING A CHARACTER ON A SUBSTRATE
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Patent #:
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|
Issue Dt:
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11/05/2002
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Application #:
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09640082
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Filing Dt:
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08/17/2000
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Title:
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OXYGEN IMPLANTATION FOR REDUCTION OF JUNCTION CAPACITANCE IN MOS TRANSISTORS
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Patent #:
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Issue Dt:
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02/19/2002
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Application #:
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09664636
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Filing Dt:
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09/19/2000
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Title:
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Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors
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|
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09667686
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Filing Dt:
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09/22/2000
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Title:
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MULTIPLE CHANNEL IMPLANTATION TO FORM RETROGRADE CHANNEL PROFILE AND TO ENGINEER THRESHOLD VOLTAGE AND SUB-SURFACE PUNCH-THROUGH
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09689144
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Filing Dt:
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10/11/2000
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Title:
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METHOD FOR SIMULTANEOUS DEPOSITION AND SPUTTERING OF TEOS AND DEVICE THEREBY FORMED
|
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