Patent Assignment Details
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| Reel/Frame: | 039706/0651 | |
| Pages: | 4 |
| | Recorded: | 09/12/2016 | | |
| Attorney Dkt #: | 16113-002USU1 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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06/29/2021
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Application #:
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15263273
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Filing Dt:
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09/12/2016
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Title:
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Flexible, Low-Latency Error Correction Architecture For Semiconductor Memory Products
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Assignee
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| 182 MAIN STREET, SUITE 304 |
| BURLINGTON, VERMONT 05401 |
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Correspondence name and address
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MORGAN S. HELLER II
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199 MAIN STREET
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P O BOX 190
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BURLINGTON, VT 05402-0190
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06/23/2024 05:39 AM
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