skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054283/0652   Pages: 6
Recorded: 11/05/2020
Attorney Dkt #:19-SC-0301US01
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
12/13/2022
Application #:
17089864
Filing Dt:
11/05/2020
Publication #:
Pub Dt:
05/05/2022
Title:
CONTROLLING TEST NETWORKS OF CHIPS USING INTEGRATED PROCESSORS
Assignors
1
Exec Dt:
10/30/2020
2
Exec Dt:
10/29/2020
3
Exec Dt:
11/04/2020
4
Exec Dt:
10/29/2020
Assignee
1
2788 SAN TOMAS EXPRESSWAY
SANTA CLARA, CALIFORNIA 95051
Correspondence name and address
PARKER JUSTISS, P.C./NVIDIA
14241 DALLAS PARKWAY
SUITE 620
DALLAS, TX 75254

Search Results as of: 06/01/2024 10:34 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT