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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036575/0670   Pages: 8
Recorded: 09/09/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 121
Page 2 of 2
Pages: 1 2
1
Patent #:
7872931
Issue Dt:
01/18/2011
Application #:
12251010
Filing Dt:
10/14/2008
Publication #:
US20100091595
Pub Dt:
04/15/2010
Title:
INTEGRATED CIRCUIT WITH CONTROL CIRCUIT FOR PERFORMING RETENTION TEST
2
Patent #:
8008729
Issue Dt:
08/30/2011
Application #:
12251864
Filing Dt:
10/15/2008
Publication #:
US20100090285
Pub Dt:
04/15/2010
Title:
INTEGRATED CIRCUIT WITH A CONTACT STRUCTURE INCLUDING A PORTION ARRANGED IN A CAVITY OF A SEMICONDUCTOR STRUCTURE
3
Patent #:
8097955
Issue Dt:
01/17/2012
Application #:
12252236
Filing Dt:
10/15/2008
Publication #:
US20100090317
Pub Dt:
04/15/2010
Title:
INTERCONNECT STRUCTURES AND METHODS
4
Patent #:
8004072
Issue Dt:
08/23/2011
Application #:
12252244
Filing Dt:
10/15/2008
Publication #:
US20100090322
Pub Dt:
04/15/2010
Title:
PACKAGING SYSTEMS AND METHODS
5
Patent #:
8294188
Issue Dt:
10/23/2012
Application #:
12252826
Filing Dt:
10/16/2008
Publication #:
US20100097835
Pub Dt:
04/22/2010
Title:
4 F2 MEMORY CELL ARRAY
6
Patent #:
7759704
Issue Dt:
07/20/2010
Application #:
12252853
Filing Dt:
10/16/2008
Publication #:
US20100096669
Pub Dt:
04/22/2010
Title:
MEMORY CELL ARRAY COMPRISING WIGGLED BIT LINES
7
Patent #:
8241989
Issue Dt:
08/14/2012
Application #:
12271313
Filing Dt:
11/14/2008
Publication #:
US20100123202
Pub Dt:
05/20/2010
Title:
INTEGRATED CIRCUIT WITH STACKED DEVICES
8
Patent #:
8797811
Issue Dt:
08/05/2014
Application #:
12273348
Filing Dt:
11/18/2008
Publication #:
US20100124130
Pub Dt:
05/20/2010
Title:
METHOD AND APPARATUS TO REDUCE POWER CONSUMPTION BY TRANSFERRING FUNCTIONALITY FROM MEMORY COMPONENTS TO A MEMORY INTERFACE
9
Patent #:
7965120
Issue Dt:
06/21/2011
Application #:
12275372
Filing Dt:
11/21/2008
Publication #:
US20100127746
Pub Dt:
05/27/2010
Title:
DIGITALLY CONTROLLED CML BUFFER
10
Patent #:
8161219
Issue Dt:
04/17/2012
Application #:
12328690
Filing Dt:
12/04/2008
Publication #:
US20100082871
Pub Dt:
04/01/2010
Title:
DISTRIBUTED COMMAND AND ADDRESS BUS ARCHITECTURE FOR A MEMORY MODULE HAVING PORTIONS OF BUS LINES SEPARATELY DISPOSED
11
Patent #:
7796449
Issue Dt:
09/14/2010
Application #:
12351023
Filing Dt:
01/09/2009
Publication #:
US20090201740
Pub Dt:
08/13/2009
Title:
INTEGRATED CIRCUIT, METHOD TO PROGRAM A MEMORY CELL ARRAY OF AN INTEGRATED CIRCUIT, AND MEMORY MODULE
12
Patent #:
7960843
Issue Dt:
06/14/2011
Application #:
12485727
Filing Dt:
06/16/2009
Publication #:
US20090321959
Pub Dt:
12/31/2009
Title:
CHIP ARRANGEMENT AND METHOD OF MANUFACTURING A CHIP ARRANGEMENT
13
Patent #:
8633053
Issue Dt:
01/21/2014
Application #:
12638674
Filing Dt:
12/15/2009
Publication #:
US20100263720
Pub Dt:
10/21/2010
Title:
PHOTOVOLTAIC DEVICE
14
Patent #:
8208294
Issue Dt:
06/26/2012
Application #:
12692044
Filing Dt:
01/22/2010
Publication #:
US20100290277
Pub Dt:
11/18/2010
Title:
RESISTIVE MEMORY CELL ACCESSED USING TWO BIT LINES
15
Patent #:
8473808
Issue Dt:
06/25/2013
Application #:
12693837
Filing Dt:
01/26/2010
Publication #:
US20110185257
Pub Dt:
07/28/2011
Title:
SEMICONDUCTOR MEMORY HAVING NON-STANDARD FORM FACTOR
16
Patent #:
8305834
Issue Dt:
11/06/2012
Application #:
12710800
Filing Dt:
02/23/2010
Publication #:
US20110205828
Pub Dt:
08/25/2011
Title:
SEMICONDUCTOR MEMORY WITH MEMORY CELL PORTIONS HAVING DIFFERENT ACCESS SPEEDS
17
Patent #:
8189374
Issue Dt:
05/29/2012
Application #:
12826201
Filing Dt:
06/29/2010
Publication #:
US20100265763
Pub Dt:
10/21/2010
Title:
MEMORY DEVICE INCLUDING AN ELECTRODE HAVING AN OUTER PORTION WITH GREATER RESISTIVITY
18
Patent #:
8098086
Issue Dt:
01/17/2012
Application #:
12939468
Filing Dt:
11/04/2010
Publication #:
US20110057699
Pub Dt:
03/10/2011
Title:
INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY
19
Patent #:
8362537
Issue Dt:
01/29/2013
Application #:
13360965
Filing Dt:
01/30/2012
Publication #:
US20120126301
Pub Dt:
05/24/2012
Title:
MEMORY DEVICES INCLUDING SEMICONDUCTOR PILLARS
20
Patent #:
8918702
Issue Dt:
12/23/2014
Application #:
13926226
Filing Dt:
06/25/2013
Publication #:
US20130290812
Pub Dt:
10/31/2013
Title:
SEMICONDUCTOR MEMORY HAVING NON-STANDARD FORM FACTOR
21
Patent #:
9412730
Issue Dt:
08/09/2016
Application #:
14096980
Filing Dt:
12/04/2013
Publication #:
US20140091367
Pub Dt:
04/03/2014
Title:
INTEGRATED CIRCUITS, STANDARD CELLS, AND METHODS FOR GENERATING A LAYOUT OF AN INTEGRATED CIRCUIT
Assignor
1
INFINEON TECHNOLOGIES AG
Exec Dt:
07/08/2015
Assignee
1
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2
DUBLIN, IRELAND
Correspondence name and address
POLARIS INNOVATIONS LIMITED
303 TERRY FOX DRIVE, SUITE 300
OTTAWA, K2K 3J1 CANADA

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