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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036575/0670   Pages: 8
Recorded: 09/09/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 121
Page 1 of 2
Pages: 1 2
1
Patent #:
7872350
Issue Dt:
01/18/2011
Application #:
11733679
Filing Dt:
04/10/2007
Publication #:
US20080251912
Pub Dt:
10/16/2008
Title:
MULTI-CHIP MODULE
2
Patent #:
7542362
Issue Dt:
06/02/2009
Application #:
11872573
Filing Dt:
10/15/2007
Publication #:
US20090097347
Pub Dt:
04/16/2009
Title:
SENSE-AMPLIFIER CIRCUIT FOR A MEMORY DEVICE WITH AN OPEN BIT LINE ARCHITECTURE
3
Patent #:
7684273
Issue Dt:
03/23/2010
Application #:
11939903
Filing Dt:
11/14/2007
Publication #:
US20090122591
Pub Dt:
05/14/2009
Title:
SENSE AMPLIFIER BIASING METHOD AND APPARATUS
4
Patent #:
7719869
Issue Dt:
05/18/2010
Application #:
11942330
Filing Dt:
11/19/2007
Publication #:
US20090129145
Pub Dt:
05/21/2009
Title:
MEMORY CELL ARRAY COMPRISING FLOATING BODY MEMORY CELLS
5
Patent #:
8116157
Issue Dt:
02/14/2012
Application #:
11943202
Filing Dt:
11/20/2007
Publication #:
US20110080796
Pub Dt:
04/07/2011
Title:
INTEGRATED CIRCUIT
6
Patent #:
8015438
Issue Dt:
09/06/2011
Application #:
11947320
Filing Dt:
11/29/2007
Publication #:
US20090144583
Pub Dt:
06/04/2009
Title:
MEMORY CIRCUIT
7
Patent #:
8144755
Issue Dt:
03/27/2012
Application #:
11947339
Filing Dt:
11/29/2007
Publication #:
US20090141843
Pub Dt:
06/04/2009
Title:
METHOD AND APPARATUS FOR DETERMINING A SKEW
8
Patent #:
8117526
Issue Dt:
02/14/2012
Application #:
11947557
Filing Dt:
11/29/2007
Publication #:
US20090110109
Pub Dt:
04/30/2009
Title:
APPARATUS AND METHOD FOR GENERATING A TRANSMIT SIGNAL AND APPARATUS AND METHOD FOR EXTRACTING AN ORIGINAL MESSAGE FROM A RECEIVED SIGNAL
9
Patent #:
7696510
Issue Dt:
04/13/2010
Application #:
11948204
Filing Dt:
11/30/2007
Publication #:
US20090046498
Pub Dt:
02/19/2009
Title:
INTEGRATED CIRCUIT INCLUDING MEMORY HAVING REDUCED CROSS TALK
10
Patent #:
8271827
Issue Dt:
09/18/2012
Application #:
11953694
Filing Dt:
12/10/2007
Publication #:
US20090150710
Pub Dt:
06/11/2009
Title:
MEMORY SYSTEM WITH EXTENDED MEMORY DENSITY CAPABILITY
11
Patent #:
7796393
Issue Dt:
09/14/2010
Application #:
11954186
Filing Dt:
12/11/2007
Publication #:
US20090135565
Pub Dt:
05/28/2009
Title:
ASSEMBLY DEVICE AND ASSEMBLY METHOD FOR A COOLING ELEMENT
12
Patent #:
7844798
Issue Dt:
11/30/2010
Application #:
11955659
Filing Dt:
12/13/2007
Publication #:
US20090158010
Pub Dt:
06/18/2009
Title:
COMMAND PROTOCOL FOR INTEGRATED CIRCUITS
13
Patent #:
7646632
Issue Dt:
01/12/2010
Application #:
11962701
Filing Dt:
12/21/2007
Publication #:
US20090161415
Pub Dt:
06/25/2009
Title:
INTEGRATED CIRCUIT FOR SETTING A MEMORY CELL BASED ON A RESET CURRENT DISTRIBUTION
14
Patent #:
8120958
Issue Dt:
02/21/2012
Application #:
11963972
Filing Dt:
12/24/2007
Publication #:
US20090161401
Pub Dt:
06/25/2009
Title:
MULTI-DIE MEMORY, APPARATUS AND MULTI-DIE MEMORY STACK
15
Patent #:
8035220
Issue Dt:
10/11/2011
Application #:
11966968
Filing Dt:
12/28/2007
Publication #:
US20090102035
Pub Dt:
04/23/2009
Title:
SEMICONDUCTOR PACKAGING DEVICE
16
Patent #:
7920433
Issue Dt:
04/05/2011
Application #:
11971819
Filing Dt:
01/09/2008
Publication #:
US20090175100
Pub Dt:
07/09/2009
Title:
METHOD AND APPARATUS FOR STORAGE DEVICE WITH A LOGIC UNIT AND METHOD FOR MANUFACTURING SAME
17
Patent #:
7785935
Issue Dt:
08/31/2010
Application #:
11983899
Filing Dt:
11/13/2007
Publication #:
US20090121314
Pub Dt:
05/14/2009
Title:
MANUFACTURING METHOD FOR FORMING AN INTEGRATED CIRCUIT DEVICE AND CORRESPONDING INTEGRATED CIRCUIT DEVICE
18
Patent #:
8344438
Issue Dt:
01/01/2013
Application #:
12023321
Filing Dt:
01/31/2008
Publication #:
US20090194410
Pub Dt:
08/06/2009
Title:
ELECTRODE OF AN INTEGRATED CIRCUIT
19
Patent #:
7903480
Issue Dt:
03/08/2011
Application #:
12023592
Filing Dt:
01/31/2008
Publication #:
US20090196110
Pub Dt:
08/06/2009
Title:
INTEGRATED CIRCUIT, AND METHOD FOR TRANSFERRING DATA
20
Patent #:
7782703
Issue Dt:
08/24/2010
Application #:
12024877
Filing Dt:
02/01/2008
Publication #:
US20090196116
Pub Dt:
08/06/2009
Title:
SEMICONDUCTOR MEMORY HAVING A BANK WITH SUB-BANKS
21
Patent #:
7888948
Issue Dt:
02/15/2011
Application #:
12026143
Filing Dt:
02/05/2008
Publication #:
US20090195258
Pub Dt:
08/06/2009
Title:
CONTROLLING AN ANALOG SIGNAL IN AN INTEGRATED CIRCUIT
22
Patent #:
7871943
Issue Dt:
01/18/2011
Application #:
12029980
Filing Dt:
02/12/2008
Publication #:
US20090200618
Pub Dt:
08/13/2009
Title:
METHOD OF MAKING TRANSISTOR GATES WITH CONTROLLED WORK FUNCTION
23
Patent #:
7737742
Issue Dt:
06/15/2010
Application #:
12031429
Filing Dt:
02/14/2008
Publication #:
US20090206896
Pub Dt:
08/20/2009
Title:
DELAY LOCKED LOOP
24
Patent #:
8120186
Issue Dt:
02/21/2012
Application #:
12032315
Filing Dt:
02/15/2008
Publication #:
US20090206461
Pub Dt:
08/20/2009
Title:
INTEGRATED CIRCUIT AND METHOD
25
Patent #:
7829879
Issue Dt:
11/09/2010
Application #:
12033519
Filing Dt:
02/19/2008
Publication #:
US20090206315
Pub Dt:
08/20/2009
Title:
INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE
26
Patent #:
7994536
Issue Dt:
08/09/2011
Application #:
12033533
Filing Dt:
02/19/2008
Publication #:
US20090206316
Pub Dt:
08/20/2009
Title:
INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE
27
Patent #:
7718464
Issue Dt:
05/18/2010
Application #:
12038846
Filing Dt:
02/28/2008
Publication #:
US20090218556
Pub Dt:
09/03/2009
Title:
INTEGRATED CIRCUIT FABRICATED USING AN OXIDIZED POLYSILICON MASK
28
Patent #:
7760546
Issue Dt:
07/20/2010
Application #:
12038850
Filing Dt:
02/28/2008
Publication #:
US20090219755
Pub Dt:
09/03/2009
Title:
INTEGRATED CIRCUIT INCLUDING AN ELECTRODE HAVING AN OUTER PORTION WITH GREATER RESISTIVITY
29
Patent #:
7876598
Issue Dt:
01/25/2011
Application #:
12039633
Filing Dt:
02/28/2008
Publication #:
US20090219756
Pub Dt:
09/03/2009
Title:
APPARATUS AND METHOD FOR DETERMINING A MEMORY STATE OF A RESISTIVE N-LEVEL MEMORY CELL AND MEMORY DEVICE
30
Patent #:
7956665
Issue Dt:
06/07/2011
Application #:
12040473
Filing Dt:
02/29/2008
Publication #:
US20090219063
Pub Dt:
09/03/2009
Title:
METHODS AND ARTICLES OF MANUFACTURE FOR OPERATING ELECTRONIC DEVICES ON A PLURALITY OF CLOCK SIGNALS
31
Patent #:
8189726
Issue Dt:
05/29/2012
Application #:
12042599
Filing Dt:
03/05/2008
Publication #:
US20090225919
Pub Dt:
09/10/2009
Title:
METHODS AND APPARATUS FOR OPERATING A DIGITAL COMMUNICATIONS INTERFACE
32
Patent #:
7969807
Issue Dt:
06/28/2011
Application #:
12042785
Filing Dt:
03/05/2008
Publication #:
US20090225616
Pub Dt:
09/10/2009
Title:
MEMORY THAT RETAINS DATA WHEN SWITCHING PARTIAL ARRAY SELF REFRESH SETTINGS
33
Patent #:
7746098
Issue Dt:
06/29/2010
Application #:
12045255
Filing Dt:
03/10/2008
Publication #:
US20090224796
Pub Dt:
09/10/2009
Title:
TERMINATION SWITCHING BASED ON DATA RATE
34
Patent #:
8606982
Issue Dt:
12/10/2013
Application #:
12045369
Filing Dt:
03/10/2008
Publication #:
US20090228624
Pub Dt:
09/10/2009
Title:
DERIVATIVE LOGICAL OUTPUT
35
Patent #:
8120985
Issue Dt:
02/21/2012
Application #:
12046870
Filing Dt:
03/12/2008
Publication #:
US20090231943
Pub Dt:
09/17/2009
Title:
MULTI-BANK MEMORY DEVICE METHOD AND APPARATUS
36
Patent #:
7843753
Issue Dt:
11/30/2010
Application #:
12051387
Filing Dt:
03/19/2008
Publication #:
US20090238020
Pub Dt:
09/24/2009
Title:
INTEGRATED CIRCUIT INCLUDING MEMORY REFRESHED BASED ON TEMPERATURE
37
Patent #:
7889589
Issue Dt:
02/15/2011
Application #:
12053913
Filing Dt:
03/24/2008
Publication #:
US20090237972
Pub Dt:
09/24/2009
Title:
MEMORY INCLUDING PERIPHERY CIRCUITRY TO SUPPORT A PORTION OR ALL OF THE MULTIPLE BANKS OF MEMORY CELLS
38
Patent #:
7783444
Issue Dt:
08/24/2010
Application #:
12056134
Filing Dt:
03/26/2008
Publication #:
US20090248337
Pub Dt:
10/01/2009
Title:
SYSTEMS AND METHODS OF ALTERNATIVE OVERLAY CALCULATION
39
Patent #:
7902876
Issue Dt:
03/08/2011
Application #:
12058671
Filing Dt:
03/29/2008
Publication #:
US20090243684
Pub Dt:
10/01/2009
Title:
METHOD AND DEVICE FOR GENERATING A DIGITAL DATA SIGNAL AND USE THEREOF
40
Patent #:
8049310
Issue Dt:
11/01/2011
Application #:
12060731
Filing Dt:
04/01/2008
Publication #:
US20090243047
Pub Dt:
10/01/2009
Title:
SEMICONDUCTOR DEVICE WITH AN INTERCONNECT ELEMENT AND METHOD FOR MANUFACTURE
41
Patent #:
8912654
Issue Dt:
12/16/2014
Application #:
12101501
Filing Dt:
04/11/2008
Publication #:
US20090256258
Pub Dt:
10/15/2009
Title:
SEMICONDUCTOR CHIP WITH INTEGRATED VIA
42
Patent #:
7973417
Issue Dt:
07/05/2011
Application #:
12105489
Filing Dt:
04/18/2008
Publication #:
US20090261480
Pub Dt:
10/22/2009
Title:
INTEGRATED CIRCUIT AND METHOD OF FABRICATING THE SAME
43
Patent #:
7781838
Issue Dt:
08/24/2010
Application #:
12106456
Filing Dt:
04/21/2008
Publication #:
US20090261411
Pub Dt:
10/22/2009
Title:
INTEGRATED CIRCUIT INCLUDING A BODY TRANSISTOR AND METHOD
44
Patent #:
7928525
Issue Dt:
04/19/2011
Application #:
12109558
Filing Dt:
04/25/2008
Publication #:
US20090267084
Pub Dt:
10/29/2009
Title:
INTEGRATED CIRCUIT WITH WIRELESS CONNECTION
45
Patent #:
8392779
Issue Dt:
03/05/2013
Application #:
12109826
Filing Dt:
04/25/2008
Publication #:
US20090271678
Pub Dt:
10/29/2009
Title:
INTERFACE VOLTAGE ADJUSTMENT BASED ON ERROR DETECTION
46
Patent #:
8054473
Issue Dt:
11/08/2011
Application #:
12112171
Filing Dt:
04/30/2008
Publication #:
US20090273773
Pub Dt:
11/05/2009
Title:
MEASUREMENT METHOD FOR DETERMINING DIMENSIONS OF FEATURES RESULTING FROM ENHANCED PATTERNING METHODS
47
Patent #:
7930654
Issue Dt:
04/19/2011
Application #:
12112835
Filing Dt:
04/30/2008
Publication #:
US20090276735
Pub Dt:
11/05/2009
Title:
SYSTEM AND METHOD OF CORRECTING ERRORS IN SEM-MEASUREMENTS
48
Patent #:
7884488
Issue Dt:
02/08/2011
Application #:
12113352
Filing Dt:
05/01/2008
Publication #:
US20090273097
Pub Dt:
11/05/2009
Title:
SEMICONDUCTOR COMPONENT WITH IMPROVED CONTACT PAD AND METHOD FOR FORMING THE SAME
49
Patent #:
8305793
Issue Dt:
11/06/2012
Application #:
12122091
Filing Dt:
05/16/2008
Publication #:
US20090285007
Pub Dt:
11/19/2009
Title:
INTEGRATED CIRCUIT WITH AN ARRAY OF RESISTANCE CHANGING MEMORY CELLS
50
Patent #:
8093696
Issue Dt:
01/10/2012
Application #:
12122215
Filing Dt:
05/16/2008
Publication #:
US20090283899
Pub Dt:
11/19/2009
Title:
SEMICONDUCTOR DEVICE
51
Patent #:
7880210
Issue Dt:
02/01/2011
Application #:
12126102
Filing Dt:
05/23/2008
Publication #:
US20090289288
Pub Dt:
11/26/2009
Title:
INTEGRATED CIRCUIT INCLUDING AN INSULATING STRUCTURE BELOW A SOURCE/DRAIN REGION AND METHOD
52
Patent #:
7893519
Issue Dt:
02/22/2011
Application #:
12128336
Filing Dt:
05/28/2008
Publication #:
US20090294895
Pub Dt:
12/03/2009
Title:
INTEGRATED CIRCUIT WITH CONDUCTIVE STRUCTURES
53
Patent #:
7659602
Issue Dt:
02/09/2010
Application #:
12131728
Filing Dt:
06/02/2008
Publication #:
US20090294907
Pub Dt:
12/03/2009
Title:
SEMICONDUCTOR COMPONENT WITH MIM CAPACITOR
54
Patent #:
7935608
Issue Dt:
05/03/2011
Application #:
12131794
Filing Dt:
06/02/2008
Publication #:
US20090294825
Pub Dt:
12/03/2009
Title:
STORAGE CELL HAVING A T-SHAPED GATE ELECTRODE AND METHOD FOR MANUFACTURING THE SAME
55
Patent #:
7773438
Issue Dt:
08/10/2010
Application #:
12134485
Filing Dt:
06/06/2008
Publication #:
US20090303813
Pub Dt:
12/10/2009
Title:
INTEGRATED CIRCUIT THAT STORES FIRST AND SECOND DEFECTIVE MEMORY CELL ADDRESSES
56
Patent #:
7940582
Issue Dt:
05/10/2011
Application #:
12134540
Filing Dt:
06/06/2008
Publication #:
US20090303814
Pub Dt:
12/10/2009
Title:
INTEGRATED CIRCUIT THAT STORES DEFECTIVE MEMORY CELL ADDRESSES
57
Patent #:
7838928
Issue Dt:
11/23/2010
Application #:
12134740
Filing Dt:
06/06/2008
Publication #:
US20090302380
Pub Dt:
12/10/2009
Title:
WORD LINE TO BIT LINE SPACING METHOD AND APPARATUS
58
Patent #:
8618600
Issue Dt:
12/31/2013
Application #:
12135318
Filing Dt:
06/09/2008
Publication #:
US20090302392
Pub Dt:
12/10/2009
Title:
INTEGRATED CIRCUIT INCLUDING A BURIED WIRING LINE
59
Patent #:
8284596
Issue Dt:
10/09/2012
Application #:
12135439
Filing Dt:
06/09/2008
Publication #:
US20090303780
Pub Dt:
12/10/2009
Title:
INTEGRATED CIRCUIT INCLUDING AN ARRAY OF DIODES COUPLED TO A LAYER OF RESISTANCE CHANGING MATERIAL
60
Patent #:
7929336
Issue Dt:
04/19/2011
Application #:
12137096
Filing Dt:
06/11/2008
Publication #:
US20090310401
Pub Dt:
12/17/2009
Title:
INTEGRATED CIRCUIT INCLUDING A MEMORY ELEMENT PROGRAMMED USING A SEED PULSE
61
Patent #:
7795109
Issue Dt:
09/14/2010
Application #:
12144482
Filing Dt:
06/23/2008
Publication #:
US20090315090
Pub Dt:
12/24/2009
Title:
ISOLATION TRENCHES WITH CONDUCTIVE PLATES
62
Patent #:
7715264
Issue Dt:
05/11/2010
Application #:
12145146
Filing Dt:
06/24/2008
Publication #:
US20090316511
Pub Dt:
12/24/2009
Title:
METHOD AND APPARATUS FOR SELECTIVELY DISABLING TERMINATION CIRCUITRY
63
Patent #:
8178927
Issue Dt:
05/15/2012
Application #:
12152471
Filing Dt:
05/14/2008
Publication #:
US20090283833
Pub Dt:
11/19/2009
Title:
INTEGRATED CIRCUITS HAVING A CONTACT STRUCTURE HAVING AN ELONGATE STRUCTURE AND METHODS FOR MANUFACTURING THE SAME
64
Patent #:
7902616
Issue Dt:
03/08/2011
Application #:
12164736
Filing Dt:
06/30/2008
Publication #:
US20090321860
Pub Dt:
12/31/2009
Title:
INTEGRATED CIRCUIT HAVING A MAGNETIC TUNNEL JUNCTION DEVICE AND METHOD
65
Patent #:
7863700
Issue Dt:
01/04/2011
Application #:
12164765
Filing Dt:
06/30/2008
Publication #:
US20090322319
Pub Dt:
12/31/2009
Title:
MAGNETORESISTIVE SENSOR WITH TUNNEL BARRIER AND METHOD
66
Patent #:
8631383
Issue Dt:
01/14/2014
Application #:
12165132
Filing Dt:
06/30/2008
Publication #:
US20090321791
Pub Dt:
12/31/2009
Title:
INTEGRATED CIRCUITS, STANDARD CELLS, AND METHODS FOR GENERATING A LAYOUT OF AN INTEGRATED CIRCUIT
67
Patent #:
7939817
Issue Dt:
05/10/2011
Application #:
12167886
Filing Dt:
07/03/2008
Publication #:
US20090050870
Pub Dt:
02/26/2009
Title:
INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH SPATIALLY STABLE MATERIAL
68
Patent #:
7791149
Issue Dt:
09/07/2010
Application #:
12170967
Filing Dt:
07/10/2008
Publication #:
US20100006953
Pub Dt:
01/14/2010
Title:
INTEGRATED CIRCUIT INCLUDING A DIELECTRIC LAYER
69
Patent #:
7838925
Issue Dt:
11/23/2010
Application #:
12173524
Filing Dt:
07/15/2008
Publication #:
US20100013005
Pub Dt:
01/21/2010
Title:
INTEGRATED CIRCUIT INCLUDING A VERTICAL TRANSISTOR AND METHOD
70
Patent #:
7893511
Issue Dt:
02/22/2011
Application #:
12175236
Filing Dt:
07/17/2008
Publication #:
US20100013035
Pub Dt:
01/21/2010
Title:
INTEGRATED CIRCUIT, MEMORY MODULE, AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT
71
Patent #:
7847415
Issue Dt:
12/07/2010
Application #:
12175726
Filing Dt:
07/18/2008
Publication #:
US20100013101
Pub Dt:
01/21/2010
Title:
METHOD FOR MANUFACTURING A MULTICHIP MODULE ASSEMBLY
72
Patent #:
7848134
Issue Dt:
12/07/2010
Application #:
12178407
Filing Dt:
07/23/2008
Publication #:
US20100020586
Pub Dt:
01/28/2010
Title:
FB DRAM MEMORY WITH STATE MEMORY
73
Patent #:
7915713
Issue Dt:
03/29/2011
Application #:
12182419
Filing Dt:
07/30/2008
Publication #:
US20100025826
Pub Dt:
02/04/2010
Title:
FIELD EFFECT TRANSISTORS WITH CHANNELS ORIENTED TO DIFFERENT CRYSTAL PLANES
74
Patent #:
8440475
Issue Dt:
05/14/2013
Application #:
12184798
Filing Dt:
08/01/2008
Publication #:
US20100030360
Pub Dt:
02/04/2010
Title:
ALIGNMENT CALCULATION
75
Patent #:
8041865
Issue Dt:
10/18/2011
Application #:
12185472
Filing Dt:
08/04/2008
Publication #:
US20100030934
Pub Dt:
02/04/2010
Title:
BUS TERMINATION SYSTEM AND METHOD
76
Patent #:
7894283
Issue Dt:
02/22/2011
Application #:
12188558
Filing Dt:
08/08/2008
Publication #:
US20100034038
Pub Dt:
02/11/2010
Title:
INTEGRATED CIRCUIT INCLUDING SELECTABLE ADDRESS AND DATA MULTIPLEXING MODE
77
Patent #:
7872902
Issue Dt:
01/18/2011
Application #:
12193267
Filing Dt:
08/18/2008
Publication #:
US20100039845
Pub Dt:
02/18/2010
Title:
INTEGRATED CIRCUIT WITH BIT LINES POSITIONED IN DIFFERENT PLANES
78
Patent #:
7646320
Issue Dt:
01/12/2010
Application #:
12193698
Filing Dt:
08/18/2008
Title:
CIRCUIT WITH SELECTABLE DATA PATHS
79
Patent #:
7848153
Issue Dt:
12/07/2010
Application #:
12194414
Filing Dt:
08/19/2008
Publication #:
US20100046266
Pub Dt:
02/25/2010
Title:
HIGH SPEED MEMORY ARCHITECTURE
80
Patent #:
7928790
Issue Dt:
04/19/2011
Application #:
12195120
Filing Dt:
08/20/2008
Publication #:
US20100045351
Pub Dt:
02/25/2010
Title:
INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY
81
Patent #:
7888665
Issue Dt:
02/15/2011
Application #:
12195964
Filing Dt:
08/21/2008
Publication #:
US20100044669
Pub Dt:
02/25/2010
Title:
INTEGRATED CIRCUIT INCLUDING MEMORY CELL HAVING CUP-SHAPED ELECTRODE INTERFACE
82
Patent #:
8334599
Issue Dt:
12/18/2012
Application #:
12196215
Filing Dt:
08/21/2008
Publication #:
US20100044877
Pub Dt:
02/25/2010
Title:
ELECTRONIC DEVICE HAVING A CHIP STACK
83
Patent #:
7859890
Issue Dt:
12/28/2010
Application #:
12200041
Filing Dt:
08/28/2008
Publication #:
US20100054021
Pub Dt:
03/04/2010
Title:
MEMORY DEVICE WITH MULTIPLE CAPACITOR TYPES
84
Patent #:
8918597
Issue Dt:
12/23/2014
Application #:
12201876
Filing Dt:
08/29/2008
Publication #:
US20100052729
Pub Dt:
03/04/2010
Title:
DIGITAL DATA INVERSION FLAG GENERATOR CIRCUIT
85
Patent #:
7899961
Issue Dt:
03/01/2011
Application #:
12202485
Filing Dt:
09/02/2008
Publication #:
US20100057971
Pub Dt:
03/04/2010
Title:
MULTI-MODE BUS INVERSION METHOD AND APPARATUS
86
Patent #:
8254166
Issue Dt:
08/28/2012
Application #:
12206439
Filing Dt:
09/08/2008
Publication #:
US20100061140
Pub Dt:
03/11/2010
Title:
INTEGRATED CIRCUIT INCLUDING DOPED SEMICONDUCTOR LINE HAVING CONDUCTIVE CLADDING
87
Patent #:
8130537
Issue Dt:
03/06/2012
Application #:
12207229
Filing Dt:
09/09/2008
Publication #:
US20100061145
Pub Dt:
03/11/2010
Title:
PHASE CHANGE MEMORY CELL WITH MOSFET DRIVEN BIPOLAR ACCESS DEVICE
88
Patent #:
7771206
Issue Dt:
08/10/2010
Application #:
12209019
Filing Dt:
09/11/2008
Publication #:
US20100062621
Pub Dt:
03/11/2010
Title:
HORIZONTAL DUAL IN-LINE MEMORY MODULES
89
Patent #:
7872936
Issue Dt:
01/18/2011
Application #:
12212400
Filing Dt:
09/17/2008
Publication #:
US20100070696
Pub Dt:
03/18/2010
Title:
SYSTEM AND METHOD FOR PACKAGED MEMORY
90
Patent #:
7796446
Issue Dt:
09/14/2010
Application #:
12234312
Filing Dt:
09/19/2008
Publication #:
US20100074038
Pub Dt:
03/25/2010
Title:
MEMORY DIES FOR FLEXIBLE USE AND METHOD FOR CONFIGURING MEMORY DIES
91
Patent #:
8495310
Issue Dt:
07/23/2013
Application #:
12235063
Filing Dt:
09/22/2008
Publication #:
US20100077157
Pub Dt:
03/25/2010
Title:
METHOD AND SYSTEM INCLUDING PLURAL MEMORY CONTROLLERS AND A MEMORY ACCESS CONTROL BUS FOR ACCESSING A MEMORY DEVICE
92
Patent #:
8914589
Issue Dt:
12/16/2014
Application #:
12235396
Filing Dt:
09/22/2008
Publication #:
US20100077139
Pub Dt:
03/25/2010
Title:
MULTI-PORT DRAM ARCHITECTURE FOR ACCESSING DIFFERENT MEMORY PARTITIONS
93
Patent #:
7755967
Issue Dt:
07/13/2010
Application #:
12240331
Filing Dt:
09/29/2008
Publication #:
US20100080075
Pub Dt:
04/01/2010
Title:
MEMORY DEVICE REFRESH METHOD AND APPARATUS
94
Patent #:
8390453
Issue Dt:
03/05/2013
Application #:
12241992
Filing Dt:
09/30/2008
Publication #:
US20100079246
Pub Dt:
04/01/2010
Title:
INTEGRATED CIRCUIT WITH A RECTIFIER ELEMENT
95
Patent #:
7863136
Issue Dt:
01/04/2011
Application #:
12242039
Filing Dt:
09/30/2008
Publication #:
US20100078711
Pub Dt:
04/01/2010
Title:
METHOD OF MANUFACTURING INTEGRATED CIRCUITS INCLUDING A FET WITH A GATE SPACER AND A FIN
96
Patent #:
8536620
Issue Dt:
09/17/2013
Application #:
12242137
Filing Dt:
09/30/2008
Publication #:
US20100078681
Pub Dt:
04/01/2010
Title:
INTEGRATED CIRCUIT INCLUDING A HETERO-INTERFACE AND SELF ADJUSTED DIFFUSION METHOD FOR MANUFACTURING THE SAME
97
Patent #:
8063394
Issue Dt:
11/22/2011
Application #:
12247763
Filing Dt:
10/08/2008
Publication #:
US20100084741
Pub Dt:
04/08/2010
Title:
INTEGRATED CIRCUIT
98
Patent #:
7791940
Issue Dt:
09/07/2010
Application #:
12248505
Filing Dt:
10/09/2008
Publication #:
US20090091976
Pub Dt:
04/09/2009
Title:
INTEGRATED CIRCUIT WITH SWITCHING UNIT FOR MEMORY CELL COUPLING, AND METHOD FOR PRODUCING AN INTEGRATED CIRCUIT FOR MEMORY CELL COUPLING
99
Patent #:
8031539
Issue Dt:
10/04/2011
Application #:
12248759
Filing Dt:
10/09/2008
Publication #:
US20100091588
Pub Dt:
04/15/2010
Title:
MEMORY DEVICE AND MEMORY SYSTEM COMPRISING A MEMORY DEVICE AND A MEMORY CONTROL DEVICE
100
Patent #:
8138538
Issue Dt:
03/20/2012
Application #:
12249060
Filing Dt:
10/10/2008
Publication #:
US20100090264
Pub Dt:
04/15/2010
Title:
INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES
Assignor
1
INFINEON TECHNOLOGIES AG
Exec Dt:
07/08/2015
Assignee
1
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2
DUBLIN, IRELAND
Correspondence name and address
POLARIS INNOVATIONS LIMITED
303 TERRY FOX DRIVE, SUITE 300
OTTAWA, K2K 3J1 CANADA

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