Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 015074/0678 | |
| Pages: | 17 |
| | Recorded: | 08/23/2004 | | |
| Conveyance: | SECURITY AGREEMENT |
|
|
Total properties:
12
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09430500
|
Filing Dt:
|
10/29/1999
|
|
Title:
|
NOVEL JFET STRUCTURE AND MANUFACTURE METHOD FOR LOW ON-RESISTANCE AND LOW VOLTAGE APPLICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2004
|
Application #:
|
09453136
|
Filing Dt:
|
12/02/1999
|
|
Title:
|
ENHANCEMENT MODE JUNCTION FIELD EFFECT TRANSISTOR WITH LOW ON RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09453141
|
Filing Dt:
|
12/02/1999
|
|
Title:
|
POWER SUPPLY MODULE IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
|
09453165
|
Filing Dt:
|
12/02/1999
|
|
Title:
|
SWITCHER FOR SWITCHING CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2001
|
Application #:
|
09458571
|
Filing Dt:
|
12/09/1999
|
|
Title:
|
COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
09676370
|
Filing Dt:
|
09/29/2000
|
|
Title:
|
CASCADE CIRCUITS UTILIZING NORMALLY-OFF JUNCTION FIELD EFFECT TRANSISTORS FOR LOW ON-RESISTANCE AND LOW VOLTAGE APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2002
|
Application #:
|
09741488
|
Filing Dt:
|
12/18/2000
|
|
Title:
|
Full wave rectifier circuit using normally off JFETs
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2005
|
Application #:
|
10153012
|
Filing Dt:
|
05/20/2002
|
|
Title:
|
JFET AND MESFET STRUCTURES FOR LOW VOLTAGE, HIGH CURRENT AND HIGH FREQUENCY APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2004
|
Application #:
|
10360450
|
Filing Dt:
|
02/05/2003
|
|
Title:
|
TWO TERMINAL RECTIFIER USING NORMALLY OFF JFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10379768
|
Filing Dt:
|
03/04/2003
|
|
Title:
|
GUARD RING STRUCTURE AND METHOD FOR FABRICATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
10683719
|
Filing Dt:
|
10/09/2003
|
|
Title:
|
STRUCTURE AND METHOD FOR ENHANCED PERFORMANCE IN SEMICONDUCTOR SUBSTRATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10728449
|
Filing Dt:
|
12/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/17/2004
| | | | |
|
Title:
|
FLIP-CHIP PACKAGING
|
|
|
Assignee
|
|
|
|
|
| 500 BLACKBURN AVENUE |
| SEWICKLEY, PENNSYLVANIA 15143 |
|
|
Correspondence name and address
|
| |
HAMILTON, BROOK, SMITH & REYNOLDS, P.C.
|
| |
DAVID J. THIBODEAU
|
| |
530 VIRGINIA ROAD, P.O. BOX 9133
|
| |
CONCORD, MA 01742-9133
|
Search Results as of:
06/19/2024 07:14 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
