Total properties:
10
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10890764
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Filing Dt:
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07/14/2004
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Publication #:
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Pub Dt:
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01/19/2006
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Title:
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AMPLITUDE CONTROL CIRCUIT
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10896547
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Filing Dt:
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07/22/2004
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Publication #:
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Pub Dt:
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12/23/2004
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Title:
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Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts
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Patent #:
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Issue Dt:
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09/04/2007
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Application #:
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11012777
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Filing Dt:
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12/14/2004
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Publication #:
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Pub Dt:
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06/15/2006
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Title:
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METHOD TO IMPROVE CURRENT AND SLEW RATE RATIO OF OFF-CHIP DRIVERS
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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11018313
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Filing Dt:
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12/21/2004
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Publication #:
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Pub Dt:
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06/22/2006
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Title:
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MEMORY ACCESS USING MULTIPLE ACTIVATED MEMORY CELL ROWS
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Patent #:
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Issue Dt:
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06/16/2009
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Application #:
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11038838
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Filing Dt:
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01/20/2005
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Publication #:
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Pub Dt:
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07/20/2006
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Title:
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METHODS OF FORMING CAPPING LAYERS ON REFLECTIVE MATERIALS
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Patent #:
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Issue Dt:
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07/31/2007
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Application #:
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11039170
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Filing Dt:
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01/20/2005
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Publication #:
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Pub Dt:
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07/20/2006
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Title:
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EUV LITHOGRAPHY FILTER
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Patent #:
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Issue Dt:
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08/22/2006
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Application #:
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11039173
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Filing Dt:
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01/20/2005
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Publication #:
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Pub Dt:
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07/20/2006
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Title:
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GATE ELECTRODE FOR FINFET DEVICE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11039293
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Filing Dt:
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01/20/2005
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Publication #:
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Pub Dt:
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07/20/2006
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Title:
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Signal redistribution using bridge layer for multichip module
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Patent #:
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Issue Dt:
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07/24/2007
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Application #:
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11039665
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Filing Dt:
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01/20/2005
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Publication #:
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Pub Dt:
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07/27/2006
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Title:
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INTERNAL REFERENCE VOLTAGE GENERATION FOR INTEGRATED CIRCUIT TESTING
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Patent #:
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Issue Dt:
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07/15/2008
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Application #:
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11040630
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Filing Dt:
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01/21/2005
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Publication #:
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Pub Dt:
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07/27/2006
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Title:
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INTEGRATED CIRCUIT INCLUDING A MEMORY HAVING LOW INITIAL LATENCY
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