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Total properties:
27
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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09629073
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Filing Dt:
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07/31/2000
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Title:
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METHOD AND APPARATUS FOR FAULT DETECTION OF A PROCESSING TOOL AND CONTROL THEREOF USING AN ADVANCED PROCESS CONTROL (APC) FRAMEWORK
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09829195
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Filing Dt:
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04/09/2001
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Title:
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DEFECT DETECTION IN PELLICIZED RETICLES VIA EXPOSURE AT SHORT WAVELENGTHS
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09894546
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Filing Dt:
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06/28/2001
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Title:
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METHOD AND APPARATUS FOR CONTROLLING PHOTOLITHOGRAPHY OVERLAY REGISTRATION
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Patent #:
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Issue Dt:
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01/09/2007
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Application #:
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10010412
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Filing Dt:
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12/07/2001
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Title:
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MASK IDENTIFICATION DATABASE SERVER
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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10010463
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Filing Dt:
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11/08/2001
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Title:
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ADJUSTABLE WAFER STAGE, AND A METHOD AND SYSTEM FOR PERFORMING PROCESS OPERATIONS USING SAME
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Patent #:
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Issue Dt:
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05/18/2004
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Application #:
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10022488
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Filing Dt:
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12/17/2001
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Title:
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METHOD AND APPARATUS FOR CONTROLLING PHOTOLITHOGRAPHY OVERLAY REGISTRATION INCORPORATING FEEDFORWARD OVERLAY INFORMATION
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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10044247
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Filing Dt:
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01/11/2002
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Title:
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SOI DEVICE WITH METAL SOURCE/DRAIN AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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06/14/2005
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Application #:
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10135145
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Filing Dt:
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04/30/2002
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Publication #:
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Pub Dt:
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12/02/2004
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Title:
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AGENT REACTIVE SCHEDULING IN AN AUTOMATED MANUFACTURING ENVIRONMENT
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Patent #:
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Issue Dt:
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08/02/2005
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Application #:
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10223174
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Filing Dt:
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08/19/2002
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Title:
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PROCESS CONTROL BASED ON AN ESTIMATED PROCESS RESULT
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Patent #:
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Issue Dt:
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08/25/2009
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Application #:
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10323529
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Filing Dt:
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12/18/2002
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Title:
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INITIATING TEST RUNS BASED ON FAULT DETECTION RESULTS
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10379738
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Filing Dt:
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03/05/2003
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Title:
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CONCURRENT MEASUREMENT OF CRITICAL DIMENSION AND OVERLAY IN SEMICONDUCTOR MANUFACTURING
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Patent #:
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Issue Dt:
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12/28/2004
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Application #:
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10427620
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Filing Dt:
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05/01/2003
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Title:
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METHOD AND APPARATUS FOR FILTERING METROLOGY DATA BASED ON COLLECTION PURPOSE
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Patent #:
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Issue Dt:
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02/28/2006
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Application #:
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10615086
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Filing Dt:
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07/07/2003
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Publication #:
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Pub Dt:
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01/13/2005
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Title:
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ULTRA-UNIFORM SILICIDES IN INTEGRATED CIRCUIT TECHNOLOGY
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|
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Patent #:
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Issue Dt:
|
07/05/2005
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Application #:
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10674400
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Filing Dt:
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10/01/2003
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Title:
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MERGED FINFET P-CHANNEL/N-CHANNEL PAIR
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Patent #:
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Issue Dt:
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05/24/2005
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Application #:
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10778411
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Filing Dt:
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02/13/2004
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Publication #:
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Pub Dt:
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08/19/2004
| | | | |
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Title:
|
METHOD AND APPARATUS FOR CONTROLLING PHOTOLITHOGRAPHY OVERLAY REGISTRATION INCORPORATING FEEDFORWARD OVERLAY INFORMATION
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Patent #:
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Issue Dt:
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02/23/2010
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Application #:
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11053935
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Filing Dt:
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02/10/2005
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Title:
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METHOD FOR FORMING SEMICONDUCTOR DEVICES WITH ACTIVE SILICON HEIGHT VARIATION
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Patent #:
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Issue Dt:
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07/27/2010
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Application #:
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11145905
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Filing Dt:
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06/06/2005
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Publication #:
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Pub Dt:
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05/04/2006
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Title:
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TECHNIQUE FOR FORMING A DIELECTRIC ETCH STOP LAYER ABOVE A STRUCTURE INCLUDING CLOSELY SPACED LINES
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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11151098
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Filing Dt:
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06/13/2005
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Publication #:
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Pub Dt:
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11/17/2005
| | | | |
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Title:
|
AGENT REACTIVE SCHEDULING IN AN AUTOMATED MANUFACTURING ENVIRONMENT
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Patent #:
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Issue Dt:
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12/11/2007
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Application #:
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11252493
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Filing Dt:
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10/17/2005
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Publication #:
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Pub Dt:
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11/30/2006
| | | | |
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Title:
|
ULTRA-UNIFORM SILICIDE SYSTEM IN INTEGRATED CIRCUIT TECHNOLOGY
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Patent #:
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Issue Dt:
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06/09/2009
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Application #:
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11535327
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Filing Dt:
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09/26/2006
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Publication #:
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Pub Dt:
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07/05/2007
| | | | |
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Title:
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AUTOMATED STATE ESTIMATION SYSTEM FOR CLUSTER TOOLS AND A METHOD OF OPERATING THE SAME
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|
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Patent #:
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|
Issue Dt:
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12/08/2009
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Application #:
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11684211
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Filing Dt:
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03/09/2007
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Publication #:
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Pub Dt:
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01/31/2008
| | | | |
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Title:
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FIELD EFFECT TRANSISTOR AND METHOD OF FORMING A FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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04/26/2011
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Application #:
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11693215
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Filing Dt:
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03/29/2007
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Publication #:
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Pub Dt:
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03/06/2008
| | | | |
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Title:
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FIELD EFFECT TRANSISTOR HAVING A STRESSED CONTACT ETCH STOP LAYER WITH REDUCED CONFORMALITY
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Patent #:
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Issue Dt:
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11/09/2010
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Application #:
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11875535
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Filing Dt:
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10/19/2007
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Publication #:
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Pub Dt:
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10/02/2008
| | | | |
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Title:
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METHOD AND SEMICONDUCTOR STRUCTURE FOR MONITORING ETCH CHARACTERISTICS DURING FABRICATION OF VIAS OF INTERCONNECT STRUCTURES
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|
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Patent #:
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Issue Dt:
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08/23/2011
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Application #:
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12691477
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Filing Dt:
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01/21/2010
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Publication #:
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Pub Dt:
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06/17/2010
| | | | |
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Title:
|
METHOD FOR FORMING SEMICONDUCTOR DEVICES WITH ACTIVE SILICON HEIGHT VARIATION
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|
|
|
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Patent #:
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|
Issue Dt:
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02/14/2012
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Application #:
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12894414
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Filing Dt:
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09/30/2010
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|
Publication #:
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Pub Dt:
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01/27/2011
| | | | |
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Title:
|
METHOD AND SEMICONDUCTOR STRUCTURE FOR MONITORING ETCH CHARACTERISTICS DURING FABRICATION OF VIAS OF INTERCONNECT STRUCTURES
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|
|
|
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Patent #:
|
|
Issue Dt:
|
09/11/2012
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Application #:
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13184050
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Filing Dt:
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07/15/2011
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|
Publication #:
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Pub Dt:
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11/10/2011
| | | | |
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Title:
|
METHOD FOR FORMING SEMICONDUCTOR DEVICES WITH ACTIVE SILICON HEIGHT VARIATION
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|
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Patent #:
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|
Issue Dt:
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07/30/2013
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Application #:
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13607023
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Filing Dt:
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09/07/2012
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Publication #:
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Pub Dt:
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12/27/2012
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Title:
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SEMICONDUCTOR DEVICES WITH ACTIVE SEMICONDUCTOR HEIGHT VARIATION
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