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Patent Assignment Details

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Reel/Frame:	009114/0695			Pages:	9
		Recorded:	05/14/1998
Conveyance:	CORRECTIVE ASSIGNMENT TO CORRECT ASSIGNOR & ASSIGNEE, PREVIOUSLY RECORDED AT REEL 8975, FRAME 0935.

Total properties: 43

Patent #:	5477082	Issue Dt:	12/19/1995	Application #:	08179904	Filing Dt:	01/11/1994
Title:	BI-PLANAR MULTI-CHIP MODULE

Patent #:	5781750	Issue Dt:	07/14/1998	Application #:	08179926	Filing Dt:	01/11/1994
Title:	DUAL-INSTRUCTION-SET ARCHITECTURE CPU WITH HIDDEN SOFTWARE EMULATION MODE

Patent #:	5442577	Issue Dt:	08/15/1995	Application #:	08207751	Filing Dt:	03/08/1994
Title:	SIGN-EXTENSION OF IMMEDIATE CONSTANTS IN AN ALU

Patent #:	5440710	Issue Dt:	08/08/1995	Application #:	08207857	Filing Dt:	03/08/1994
Title:	EMULATION OF SEGMENT BOUNDS CHECKING USING PAGING WITH SUB-PAGE VALIDITY

Patent #:	5511017	Issue Dt:	04/23/1996	Application #:	08252579	Filing Dt:	06/01/1994
Title:	REDUCED-MODULUS ADDRESS GENERATION USING SIGN-EXTENSION AND CORRECTION

Patent #:	5551001	Issue Dt:	08/27/1996	Application #:	08267658	Filing Dt:	06/29/1994
Title:	MASTER-SLAVE CACHE SYSTEM FOR INSTRUCTION AND DATA CACHE MEMORIES

Patent #:	5481684	Issue Dt:	01/02/1996	Application #:	08277905	Filing Dt:	07/20/1994
Title:	EMULATING OPERATING SYSTEM CALLS IN AN ALTERNATE INSTRUCTION SET USING A MODIFIED CODE SEGMENT DESCRIPTOR

Patent #:	5481693	Issue Dt:	01/02/1996	Application #:	08277962	Filing Dt:	07/20/1994
Title:	SHARED REGISTER ARCHITECTURE FOR A DUAL-INSTRUCTION-SET CPU

Patent #:	5598546	Issue Dt:	01/28/1997	Application #:	08298583	Filing Dt:	08/31/1994
Title:	DUAL-ARCHITECTURE SUPER-SCALAR PIPELINE

Patent #:	5453949	Issue Dt:	09/26/1995	Application #:	08298593	Filing Dt:	08/31/1994
Title:	BICMOS STATIC RAM WITH ACTIVE-LOW WORD LINE

Patent #:	5542109	Issue Dt:	07/30/1996	Application #:	08298771	Filing Dt:	08/31/1994
Title:	ADDRESS TRACKING AND BRANCH RESOLUTION IN A PROCESSOR WITH MULTIPLE EXECUTION PIPELINES AND INSTRUCTION STREAM DISCONTINUITIES

Patent #:	5608886	Issue Dt:	03/04/1997	Application #:	08298778	Filing Dt:	08/31/1994
Title:	BLOCK-BASED BRANCH PREDICTION USING A TARGET FINDER ARRAY STORING TAR- GET SUB-ADDRESSES

Patent #:	5574677	Issue Dt:	11/12/1996	Application #:	08344179	Filing Dt:	11/23/1994
Title:	ADAPTIVE NON-RESTORING INTEGER DIVIDE APPARATUS WITH INTEGRATED OVERFLOW DETECT

Patent #:	5644752	Issue Dt:	07/01/1997	Application #:	08350815	Filing Dt:	12/07/1994
Title:	COMBINED STORE QUEUE FOR A MASTER-SLAVE CACHE SYSTEM

Patent #:	5542059	Issue Dt:	07/30/1996	Application #:	08361017	Filing Dt:	12/21/1994
Title:	DUAL INSTRUCTION SET PROCESSOR HAVING A PIPELINE WITH A PIPESTAGE FUNCTIONAL UNIT THAT IS RELOCATABLE IN TIME AND SEQUENCE ORDER

Patent #:	5548545	Issue Dt:	08/20/1996	Application #:	08375352	Filing Dt:	01/19/1995
Title:	FLOATING POINT EXCEPTION PREDICTION FOR COMPOUND OPERATIONS AND VARIABLE PRECISION USING AN INTERMEDIATE EXPONENT BUS

Patent #:	5477489	Issue Dt:	12/19/1995	Application #:	08407505	Filing Dt:	03/20/1995
Title:	HIGH-STABILITY CMOS MULTI-PORT REGISTER FILE MEMORY CELL WITH COLUMN ISOLATION AND CURRENT-MIRROR ROW LINE DRIVER

Patent #:	5634118	Issue Dt:	05/27/1997	Application #:	08419122	Filing Dt:	04/10/1995
Title:	SPLITTING A FLOATING-POINT STACK-EXCHANGE INSTRUCTION FOR MERGING INTO SURROUNDING INSTRUCTIONS BY OPERAND TRANSLATION

Patent #:	5884057	Issue Dt:	03/16/1999	Application #:	08436135	Filing Dt:	05/08/1995
Title:	TEMPORAL RE-ALIGNMENT OF A FLOATING POINT PIPELINE TO AN INTEGER PIPELINE FOR EMULATION OF A LOAD-OPERATE ARCHITECTURE ON A LOAD/STORE PROCESSOR

Patent #:	5664159	Issue Dt:	09/02/1997	Application #:	08436136	Filing Dt:	05/08/1995
Title:	METHOD FOR EMULATING MULTIPLE DEBUG BREAKPOINTS BY PAGE PARTITIONING USING A SINGLE BREAKPOINT REGISTER

Patent #:	5652872	Issue Dt:	07/29/1997	Application #:	08436137	Filing Dt:	05/08/1995
Title:	TRANSLATOR HAVING SEGMENT BOUNDS ENCODING FOR STORAGE IN A TLB

Patent #:	5598553	Issue Dt:	01/28/1997	Application #:	08444813	Filing Dt:	05/18/1995
Title:	EMULATION OF PROGRAM WATCHPOINT CHECKING USING PAGING WITH SUB-PAGE VALIDITY

Patent #:	5497341	Issue Dt:	03/05/1996	Application #:	08444814	Filing Dt:	05/18/1995
Title:	SIGN-EXTENSION OF IMMEDIATE CONSTANTS IN AN ALU USING AN ADDER IN AN I NTEGER

Patent #:	5805918	Issue Dt:	09/08/1998	Application #:	08547395	Filing Dt:	10/24/1995
Title:	DUAL-INSTRUCTION-SET CPU HAVING SHARED REGISTER FOR STORING DATA BEFORE SWITCHING TO THE ALTERNATE INSTRUCTION SET

Patent #:	5633819	Issue Dt:	05/27/1997	Application #:	08547396	Filing Dt:	10/24/1995
Title:	INEXACT LEADING-ONE/LEADING-ZERO PREDICTION INTEGRATED WITH A FLOATING-POINT ADDER

Patent #:	5809272	Issue Dt:	09/15/1998	Application #:	08564718	Filing Dt:	11/29/1995
Title:	EARLY INSTRUCTION-LENGTH PRE-DECODE OF VARIABLE-LENGTH INSTRUCTIONS IN A SUPERSCALAR PROCESSOR

Patent #:	5685009	Issue Dt:	11/04/1997	Application #:	08564719	Filing Dt:	11/29/1995
Title:	SHARED FLOATING-POINT REGISTERS AND REGISTER PORT-PAIRING IN A DUAL-ARCHITECTURE CPU

Patent #:	5828578	Issue Dt:	10/27/1998	Application #:	08564721	Filing Dt:	11/29/1995
Title:	MICROPROCESSOR WITH A LARGE CACHE SHARED BY REDUNDANT CPUS FOR INCREASING MANUFACTURING YIELD

Patent #:	5687336	Issue Dt:	11/11/1997	Application #:	08584836	Filing Dt:	01/11/1996
Title:	STACK PUSH/POP TRACKING AND PAIRING IN A PIPELINED PROCESSOR

Patent #:	5751614	Issue Dt:	05/12/1998	Application #:	08609908	Filing Dt:	02/29/1996
Title:	SIGN-EXTENSION MERGE/MASK, ROTATE/SHIFT, AND BOOLEAN OPERATIONS EXECUTED IN A VECTORED MUX ON AN ALU

Patent #:	5790443	Issue Dt:	08/04/1998	Application #:	08618632	Filing Dt:	03/19/1996
Title:	MIXED-MODULO ADDRESS GENERATION USING SHADOW SEGMENT REGISTERS

Patent #:	5790826	Issue Dt:	08/04/1998	Application #:	08618636	Filing Dt:	03/19/1996
Title:	REDUCED REGISTER-DEPENDENCY CHECKING FOR PAIRED-INSTRUCTION DISPATCH IN A SUPERSCALAR PROCESSOR WITH PARTIAL REGISTER WRITES

Patent #:	5784590	Issue Dt:	07/21/1998	Application #:	08618637	Filing Dt:	03/19/1996
Title:	SLAVE CACHE HAVING SUB-LINE VALID BITS UPDATED BY A MASTER CACHE

Patent #:	5692152	Issue Dt:	11/25/1997	Application #:	08649115	Filing Dt:	05/14/1996
Title:	MASTER-SLAVE CACHE SYSTEM WITH DE-COUPLED DATA AND TAG PIPELINES AND LOOP-BACK

Patent #:	5781457	Issue Dt:	07/14/1998	Application #:	08649116	Filing Dt:	05/14/1996
Title:	MERGE/MASK, ROTATE/SHIFT, AND BOOLEAN OPERATIONS FROM TWO INSTRUCTION SETS EXECUTED IN A VECTORED MUX ON A DUAL-ALU

Patent #:	5732209	Issue Dt:	03/24/1998	Application #:	08649117	Filing Dt:	05/14/1996
Title:	SELF-TESTING MULTI-PROCESSOR DIE WITH INTERNAL COMPARE POINTS

Patent #:	5822602	Issue Dt:	10/13/1998	Application #:	08685141	Filing Dt:	07/23/1996
Title:	PIPELINDED PROCESSOR FOR EXECUTING REPEATED STRING INSTRUCTIONS BY HALTING DISPATCH AFTER COMPARISON TO PIPELINE CAPACITY

Patent #:	5745913	Issue Dt:	04/28/1998	Application #:	08691005	Filing Dt:	08/05/1996
Title:	MULTI-PROCESSOR DRAM CONTROLLER THAT PRIORITIZES ROW-MISS REQUESTS TO STALE BANKS

Patent #:	5848264	Issue Dt:	12/08/1998	Application #:	08740248	Filing Dt:	10/25/1996
Title:	DEBUG AND VIDEO QUEUE FOR MULTI-PROCESSOR CHIP

Patent #:	5935198	Issue Dt:	08/10/1999	Application #:	08755545	Filing Dt:	11/22/1996
Title:	MULTIPLIER WITH SELECTABLE BOOTH ENCODERS FOR PERFORMING 3D GRAPHICS INTERPOLATIONS WITH TWO MULTIPLIES IN A SINGLE PASS THROUGH THE MULTIPLIER

Patent #:	5826074	Issue Dt:	10/20/1998	Application #:	08755547	Filing Dt:	11/22/1996
Title:	EXTENSTION OF 32-BIT ARCHITECTURE FOR 64-BIT ADDRESSING WITH SHARED SUPER-PAGE REGISTER

Patent #:	5951702	Issue Dt:	09/14/1999	Application #:	08832922	Filing Dt:	04/04/1997
Title:	RAM-LIKE TEST STRUCTURE SUPERIMPOSED OVER ROWS OF MACROCELLS WITH ADDED DIFFERENTIAL PASS TRANSISTORS IN A CPU

Patent #:	5757690	Issue Dt:	05/26/1998	Application #:	08842007	Filing Dt:	04/23/1997
Title:	EMBEDDED ROM WITH RAM VALID BITS FOR FETCHING ROM-CODE UPDATES FROM EXTERNAL MEMORY

Assignor

EXPONENTIAL TECHNOLOGY, INC.

Exec Dt:

09/02/1997

Assignee

S3 INCORPORATED

P.O. BOX 58058

2801 MISSION COLLEGE BOULEVARD

SANTA CLARA, CALIFORNIA 95052

Correspondence name and address
	FENWICK & WEST LLP
	GREG T. SUEOKA, ESQ.
	TWO PALO ALTO SQUARE
	PALO ALTO, CA 94306

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