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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Total properties: 11

Patent #:	6016539	Issue Dt:	01/18/2000	Application #:	08963345	Filing Dt:	11/03/1997
Title:	DATAPATH CONTROL LOGIC FOR PROCESSORS HAVING INSTRUCTION SET ARCHITECTURES IMPLEMENTED WITH HIERARCHICALLY ORGANIZED PRIMITIVE OPERATIONS

Patent #:	5923894	Issue Dt:	07/13/1999	Application #:	08963346	Filing Dt:	11/03/1997
Title:	ADAPTABLE INPUT/OUTPUT PIN CONTROL

Patent #:	5940626	Issue Dt:	08/17/1999	Application #:	08963387	Filing Dt:	11/03/1997
Title:	PROCESSOR HAVING AN INSTRUCTION SET ARCHITECTURE IMPLEMENTED WITH HIERARCHICALLY ORGANIZED PRIMITIVE OPERATIONS

Patent #:	6067601	Issue Dt:	05/23/2000	Application #:	08963389	Filing Dt:	11/03/1997
Title:	CACHE MEMORY BASED INSTRUCTION EXECUTION

Patent #:	6178482	Issue Dt:	01/23/2001	Application #:	08963391	Filing Dt:	11/03/1997
Title:	VIRTUAL REGISTER SETS

Patent #:	6216218	Issue Dt:	04/10/2001	Application #:	09120041	Filing Dt:	07/21/1998
Title:	PROCESSOR HAVING A DATAPATH AND CONTROL LOGIC CONSTITUTED WITH BASIS EXECUTION BLOCKS

Patent #:	6438679	Issue Dt:	08/20/2002	Application #:	09120043	Filing Dt:	07/21/1998
Publication #:	US20020053013	Pub Dt:	05/02/2002
Title:	MULTIPLE ISA SUPPORT BY A PROCESSOR USING PRIMITIVE OPERATIONS

Patent #:	6327632	Issue Dt:	12/04/2001	Application #:	09231942	Filing Dt:	01/14/1999
Title:	ADAPTABLE I/O PINS MANIFESTING I/O CHARACTERISTICS RESPONSIVE TO BIT VALUES STORED IN SELECTED ADDRESSABLE STORGE LOCATIONS, EACH PIN COUPLED TO THREE CORRESONDING ADDRESSABLE STORAGE LOCATIONS

Patent #:	6308254	Issue Dt:	10/23/2001	Application #:	09442848	Filing Dt:	11/18/1999
Title:	PROCESSING INSTRUCTIONS OF AN INSTRUCTION SET ARCHITECTURE BY EXECUTING HIERARCHICALLY ORGANIZED SNIPPETS OF ATOMIC UNITS OF PRIMITIVE OPERATIONS

Patent #:	6505291	Issue Dt:	01/07/2003	Application #:	09697911	Filing Dt:	10/26/2000
Title:	PROCESSOR HAVING A DATAPATH AND CONTROL LOGIC CONSTITUTED WITH BASIS EXECUTION BLOCKS

Patent #:	6677786	Issue Dt:	01/13/2004	Application #:	10086500	Filing Dt:	02/28/2002
Publication #:	US20030042506	Pub Dt:	03/06/2003
Title:	MULTI-SERVICE PROCESSOR CLOCKING SYSTEM

Assignor

Exec Dt:

07/14/2009

Assignee

101 UNIVERSITY AVE

STE 100

PALO ALTO, CALIFORNIA 94301

Correspondence name and address
	UCC DIRECT SERVICES
	ATTN: 14080632
	187 WOLF ROAD, SUITE 101
	ALBANY, NY 12205

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