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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	056702/0712			Pages:	7
		Recorded:	06/29/2021
Conveyance:	MERGER AND CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).

Total properties: 92

Patent #:	7260591	Issue Dt:	08/21/2007	Application #:	10781031	Filing Dt:	02/17/2004
Publication #:	US20040172431	Pub Dt:	09/02/2004
Title:	METHOD FOR SYNTHESIZING LINEAR FINITE STATE MACHINES

Patent #:	7496864	Issue Dt:	02/24/2009	Application #:	10930235	Filing Dt:	08/30/2004
Publication #:	US20050028135	Pub Dt:	02/03/2005
Title:	INTERACTIVE LOOP CONFIGURATION IN A BEHAVIORAL SYNTHESIS TOOL

Patent #:	7590963	Issue Dt:	09/15/2009	Application #:	10983132	Filing Dt:	11/08/2004
Publication #:	US20050114865	Pub Dt:	05/26/2005
Title:	INTEGRATING MULTIPLE ELECTRONIC DESIGN APPLICATIONS

Patent #:	7721174	Issue Dt:	05/18/2010	Application #:	10985539	Filing Dt:	11/09/2004
Publication #:	US20050066247	Pub Dt:	03/24/2005
Title:	FULL-SPEED BIST CONTROLLER FOR TESTING EMBEDDED SYNCHRONOUS MEMORIES

Patent #:	7072997	Issue Dt:	07/04/2006	Application #:	11015407	Filing Dt:	12/17/2004
Publication #:	US20050105551	Pub Dt:	05/19/2005
Title:	ASYMMETRIC DATA PATH MEDIA ACCESS CONTROLLER

Patent #:	7437640	Issue Dt:	10/14/2008	Application #:	11213672	Filing Dt:	08/25/2005
Publication #:	US20060041814	Pub Dt:	02/23/2006
Title:	FAULT DIAGNOSIS OF COMPRESSED TEST RESPONSES HAVING ONE OR MORE UNKNOWN STATES

Patent #:	7424660	Issue Dt:	09/09/2008	Application #:	11397822	Filing Dt:	04/03/2006
Publication #:	US20060190789	Pub Dt:	08/24/2006
Title:	SYNCHRONIZATION POINT ACROSS DIFFERENT MEMORY BIST CONTROLLERS

Patent #:	7844944	Issue Dt:	11/30/2010	Application #:	11517637	Filing Dt:	09/08/2006
Publication #:	US20070006125	Pub Dt:	01/04/2007
Title:	HIERARCHICAL PRESENTATION TECHNIQUES FOR A DESIGN TOOL

Patent #:	7712050	Issue Dt:	05/04/2010	Application #:	11517638	Filing Dt:	09/08/2006
Publication #:	US20070006112	Pub Dt:	01/04/2007
Title:	HIERARCHICAL PRESENTATION TECHNIQUES FOR A DESIGN TOOL

Patent #:	7509546	Issue Dt:	03/24/2009	Application #:	11523111	Filing Dt:	09/18/2006
Publication #:	US20070016836	Pub Dt:	01/18/2007
Title:	TEST PATTERN COMPRESSION FOR AN INTEGRATED CIRCUIT TEST ENVIRONMENT

Patent #:	7698664	Issue Dt:	04/13/2010	Application #:	11751511	Filing Dt:	05/21/2007
Publication #:	US20070266445	Pub Dt:	11/15/2007
Title:	SECURE EXCHANGE OF INFORMATION IN ELECTRONIC DESIGN AUTOMATION

Patent #:	8301414	Issue Dt:	10/30/2012	Application #:	11772648	Filing Dt:	07/02/2007
Publication #:	US20070283202	Pub Dt:	12/06/2007
Title:	COMPACTOR INDEPENDENT FAULT DIAGNOSIS

Patent #:	7788622	Issue Dt:	08/31/2010	Application #:	11869897	Filing Dt:	10/10/2007
Publication #:	US20080034342	Pub Dt:	02/07/2008
Title:	DISTRIBUTED AUTOROUTING OF CONDUCTIVE PATHS

Patent #:	8024387	Issue Dt:	09/20/2011	Application #:	11894393	Filing Dt:	08/20/2007
Publication #:	US20070294327	Pub Dt:	12/20/2007
Title:	METHOD FOR SYNTHESIZING LINEAR FINITE STATE MACHINES

Patent #:	7549100	Issue Dt:	06/16/2009	Application #:	11925700	Filing Dt:	10/26/2007
Publication #:	US20080059842	Pub Dt:	03/06/2008
Title:	DYNAMIC VERIFICATION TRAVERSAL STRATEGIES

Patent #:	7743302	Issue Dt:	06/22/2010	Application #:	12012039	Filing Dt:	01/30/2008
Publication #:	US20080133987	Pub Dt:	06/05/2008
Title:	COMPRESSING TEST RESPONSES USING A COMPACTOR

Patent #:	7710755	Issue Dt:	05/04/2010	Application #:	12018996	Filing Dt:	01/24/2008
Publication #:	US20080137391	Pub Dt:	06/12/2008
Title:	DRAM ARCHITECTURE

Patent #:	7945871	Issue Dt:	05/17/2011	Application #:	12145433	Filing Dt:	06/24/2008
Publication #:	US20080256500	Pub Dt:	10/16/2008
Title:	INTEGRATED OPC VERIFICATION TOOL

Patent #:	8146030	Issue Dt:	03/27/2012	Application #:	12353210	Filing Dt:	01/13/2009
Publication #:	US20090172634	Pub Dt:	07/02/2009
Title:	INTERACTIVE LOOP CONFIGURATION IN A BEHAVIORAL SYNTHESIS TOOL

Patent #:	7805649	Issue Dt:	09/28/2010	Application #:	12396377	Filing Dt:	03/02/2009
Publication #:	US20090228749	Pub Dt:	09/10/2009
Title:	METHOD AND APPARATUS FOR SELECTIVELY COMPACTING TEST RESPONSES

Patent #:	7865794	Issue Dt:	01/04/2011	Application #:	12402880	Filing Dt:	03/12/2009
Publication #:	US20090177933	Pub Dt:	07/09/2009
Title:	DECOMPRESSOR/PRPG FOR APPLYING PSEUDO-RANDOM AND DETERMINISTIC TEST PATTERNS

Patent #:	7900104	Issue Dt:	03/01/2011	Application #:	12405409	Filing Dt:	03/17/2009
Publication #:	US20090259900	Pub Dt:	10/15/2009
Title:	TEST PATTERN COMPRESSION FOR AN INTEGRATED CIRCUIT TEST ENVIRONMENT

Patent #:	7962820	Issue Dt:	06/14/2011	Application #:	12405828	Filing Dt:	03/17/2009
Publication #:	US20090249147	Pub Dt:	10/01/2009
Title:	FAULT DIAGNOSIS OF COMPRESSED TEST RESPONSES

Patent #:	7653851	Issue Dt:	01/26/2010	Application #:	12412267	Filing Dt:	03/26/2009
Publication #:	US20090187800	Pub Dt:	07/23/2009
Title:	PHASE SHIFTER WITH REDUCED LINEAR DEPENDENCY

Patent #:	8108806	Issue Dt:	01/31/2012	Application #:	12501349	Filing Dt:	07/10/2009
Publication #:	US20090271759	Pub Dt:	10/29/2009
Title:	CONTRAST-BASED RESOLUTION ENHANCEMENT FOR PHOTOLITHOGRAPHIC PROCESSING

Patent #:	7805651	Issue Dt:	09/28/2010	Application #:	12633601	Filing Dt:	12/08/2009
Publication #:	US20100083063	Pub Dt:	04/01/2010
Title:	PHASE SHIFTER WITH REDUCED LINEAR DEPENDENCY

Patent #:	7949990	Issue Dt:	05/24/2011	Application #:	12754850	Filing Dt:	04/06/2010
Publication #:	US20100199240	Pub Dt:	08/05/2010
Title:	PARALLEL ELECTRONIC DESIGN AUTOMATION: SHARED SIMULTANEOUS EDITING

Patent #:	8302039	Issue Dt:	10/30/2012	Application #:	12758640	Filing Dt:	04/12/2010
Publication #:	US20100199107	Pub Dt:	08/05/2010
Title:	SECURE EXCHANGE OF INFORMATION IN ELECTRONIC DESIGN AUTOMATION

Patent #:	8438516	Issue Dt:	05/07/2013	Application #:	12773462	Filing Dt:	05/04/2010
Publication #:	US20100287524	Pub Dt:	11/11/2010
Title:	METASTABILITY EFFECTS SIMULATION FOR A CIRCUIT DESCRIPTION

Patent #:	8280688	Issue Dt:	10/02/2012	Application #:	12790049	Filing Dt:	05/28/2010
Publication #:	US20100306606	Pub Dt:	12/02/2010
Title:	COMPACTOR INDEPENDENT DIRECT DIAGNOSIS OF TEST HARDWARE

Patent #:	8046653	Issue Dt:	10/25/2011	Application #:	12854786	Filing Dt:	08/11/2010
Publication #:	US20100306609	Pub Dt:	12/02/2010
Title:	LOW POWER DECOMPRESSION OF TEST CUBES

Patent #:	8108743	Issue Dt:	01/31/2012	Application #:	12891498	Filing Dt:	09/27/2010
Publication #:	US20110138242	Pub Dt:	06/09/2011
Title:	METHOD AND APPARATUS FOR SELECTIVELY COMPACTING TEST RESPONSES

Patent #:	8645880	Issue Dt:	02/04/2014	Application #:	12945674	Filing Dt:	11/12/2010
Publication #:	US20110119643	Pub Dt:	05/19/2011
Title:	SUM OF COHERENT SYSTEMS (SOCS) APPROXIMATION BASED ON OBJECT INFORMATION

Patent #:	8522197	Issue Dt:	08/27/2013	Application #:	12956738	Filing Dt:	11/30/2010
Publication #:	US20110138348	Pub Dt:	06/09/2011
Title:	HIERARCHICAL PRESENTATION TECHNIQUES FOR A DESIGN TOOL

Patent #:	8566753	Issue Dt:	10/22/2013	Application #:	12972097	Filing Dt:	12/17/2010
Publication #:	US20110161894	Pub Dt:	06/30/2011
Title:	FRAGMENTATION POINT AND SIMULATION SITE ADJUSTMENT FOR RESOLUTION ENHANCEMENT TECHNIQUES

Patent #:	8533547	Issue Dt:	09/10/2013	Application #:	13013712	Filing Dt:	01/25/2011
Publication #:	US20110214026	Pub Dt:	09/01/2011
Title:	CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES

Patent #:	9652574	Issue Dt:	05/16/2017	Application #:	13093828	Filing Dt:	04/25/2011
Publication #:	US20110289471	Pub Dt:	11/24/2011
Title:	Simultaneous Multi-Layer Fill Generation

Patent #:	8301945	Issue Dt:	10/30/2012	Application #:	13225240	Filing Dt:	09/02/2011
Publication #:	US20110320999	Pub Dt:	12/29/2011
Title:	DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS

Patent #:	10089432	Issue Dt:	10/02/2018	Application #:	13304094	Filing Dt:	11/23/2011
Publication #:	US20180260511	Pub Dt:	09/13/2018
Title:	DESIGN-RULE-CHECK WAIVER

Patent #:	8468475	Issue Dt:	06/18/2013	Application #:	13400510	Filing Dt:	02/20/2012
Publication #:	US20120151424	Pub Dt:	06/14/2012
Title:	CONVERSION OF CIRCUIT DESCRIPTION TO AN ABSTRACT MODEL OF THE CIRCUIT

Patent #:	8719742	Issue Dt:	05/06/2014	Application #:	13400521	Filing Dt:	02/20/2012
Publication #:	US20120150522	Pub Dt:	06/14/2012
Title:	CONVERSION OF CIRCUIT DESCRIPTION TO AN ABSTRACT MODEL OF THE CIRCUIT

Patent #:	8650522	Issue Dt:	02/11/2014	Application #:	13448116	Filing Dt:	04/16/2012
Publication #:	US20120204139	Pub Dt:	08/09/2012
Title:	DETERMINING MUTUAL INDUCTANCE BETWEEN INTENTIONAL INDUCTORS

Patent #:	8732648	Issue Dt:	05/20/2014	Application #:	13525107	Filing Dt:	06/15/2012
Publication #:	US20120254814	Pub Dt:	10/04/2012
Title:	HIGH-FREQUENCY VLSI INTERCONNECT AND INTENTIONAL INDUCTOR IMPEDANCE EXTRACTION IN THE PRESENCE OF A MULTI-LAYER CONDUCTIVE SUBSTRATE

Patent #:	8839164	Issue Dt:	09/16/2014	Application #:	13600074	Filing Dt:	08/30/2012
Publication #:	US20130232460	Pub Dt:	09/05/2013
Title:	Power State Transition Verification For Electronic Design

Patent #:	8621402	Issue Dt:	12/31/2013	Application #:	13617263	Filing Dt:	09/14/2012
Publication #:	US20130139117	Pub Dt:	05/30/2013
Title:	MODEL-BASED FILL

Patent #:	8843859	Issue Dt:	09/23/2014	Application #:	13649962	Filing Dt:	10/11/2012
Publication #:	US20130036390	Pub Dt:	02/07/2013
Title:	Layout Content Analysis for Source Mask Optimization Acceleration

Patent #:	8713487	Issue Dt:	04/29/2014	Application #:	13737363	Filing Dt:	01/09/2013
Publication #:	US20130191792	Pub Dt:	07/25/2013
Title:	SUB-RESOLUTION ASSIST FEATURE REPAIR

Patent #:	8713488	Issue Dt:	04/29/2014	Application #:	13740639	Filing Dt:	01/14/2013
Publication #:	US20130198700	Pub Dt:	08/01/2013
Title:	Layout Design Defect Repair Based On Inverse Lithography And Traditional Optical Proximity Correction

Patent #:	8788982	Issue Dt:	07/22/2014	Application #:	13740651	Filing Dt:	01/14/2013
Publication #:	US20130191795	Pub Dt:	07/25/2013
Title:	Layout Design Defect Repair Using Inverse Lithography

Patent #:	9262557	Issue Dt:	02/16/2016	Application #:	13858650	Filing Dt:	04/08/2013
Publication #:	US20130239084	Pub Dt:	09/12/2013
Title:	MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING

Patent #:	9135376	Issue Dt:	09/15/2015	Application #:	13875143	Filing Dt:	05/01/2013
Publication #:	US20130298102	Pub Dt:	11/07/2013
Title:	INPUT SPACE REDUCTION FOR VERIFICATION TEST SET GENERATION

Patent #:	8914761	Issue Dt:	12/16/2014	Application #:	13888036	Filing Dt:	05/06/2013
Publication #:	US20130246985	Pub Dt:	09/19/2013
Title:	METASTABILITY EFFECTS SIMULATION FOR A CIRCUIT DESCRIPTION

Patent #:	9003248	Issue Dt:	04/07/2015	Application #:	13919998	Filing Dt:	06/17/2013
Publication #:	US20140372820	Pub Dt:	12/18/2014
Title:	Fault-Driven Scan Chain Configuration For Test-Per-Clock

Patent #:	10379161	Issue Dt:	08/13/2019	Application #:	13920004	Filing Dt:	06/17/2013
Publication #:	US20140372821	Pub Dt:	12/18/2014
Title:	SCAN CHAIN STITCHING FOR TEST-PER-CLOCK

Patent #:	8863051	Issue Dt:	10/14/2014	Application #:	13946941	Filing Dt:	07/19/2013
Publication #:	US20130305204	Pub Dt:	11/14/2013
Title:	HIERARCHICAL FEATURE EXTRACTION FOR ELECTRICAL INTERACTION CALCULATIONS

Patent #:	8832609	Issue Dt:	09/09/2014	Application #:	13947839	Filing Dt:	07/22/2013
Publication #:	US20130305195	Pub Dt:	11/14/2013
Title:	ANALYSIS OPTIMIZER

Patent #:	9355201	Issue Dt:	05/31/2016	Application #:	13970281	Filing Dt:	08/19/2013
Publication #:	US20140053123	Pub Dt:	02/20/2014
Title:	DENSITY-BASED INTEGRATED CIRCUIT DESIGN ADJUSTMENT

Patent #:	9134370	Issue Dt:	09/15/2015	Application #:	14021800	Filing Dt:	09/09/2013
Publication #:	US20140006888	Pub Dt:	01/02/2014
Title:	CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES

Patent #:	8826204	Issue Dt:	09/02/2014	Application #:	14042279	Filing Dt:	09/30/2013
Publication #:	US20140033164	Pub Dt:	01/30/2014
Title:	MUTUAL INDUCTANCE EXTRACTION USING DIPOLE APPROXIMATIONS

Patent #:	9304881	Issue Dt:	04/05/2016	Application #:	14055182	Filing Dt:	10/16/2013
Publication #:	US20140046650	Pub Dt:	02/13/2014
Title:	TRACE ROUTING NETWORK

Patent #:	9361422	Issue Dt:	06/07/2016	Application #:	14059183	Filing Dt:	10/21/2013
Publication #:	US20140143741	Pub Dt:	05/22/2014
Title:	FRAGMENTATION POINT AND SIMULATION SITE ADJUSTMENT FOR RESOLUTION ENHANCEMENT TECHNIQUES

Patent #:	9026423	Issue Dt:	05/05/2015	Application #:	14141235	Filing Dt:	12/26/2013
Publication #:	US20140108865	Pub Dt:	04/17/2014
Title:	FAULT SUPPORT IN AN EMULATION ENVIRONMENT

Patent #:	8947954	Issue Dt:	02/03/2015	Application #:	14145677	Filing Dt:	12/31/2013
Publication #:	US20140112083	Pub Dt:	04/24/2014
Title:	RANDOM ACCESS MEMORY FOR USE IN AN EMULATION ENVIRONMENT

Patent #:	9134374	Issue Dt:	09/15/2015	Application #:	14222362	Filing Dt:	03/21/2014
Publication #:	US20140208178	Pub Dt:	07/24/2014
Title:	Circuit and Method for Measuring Delays between Edges of Signals of a Circuit

Patent #:	8910108	Issue Dt:	12/09/2014	Application #:	14247078	Filing Dt:	04/07/2014
Publication #:	US20140223401	Pub Dt:	08/07/2014
Title:	HIGH-FREQUENCY VLSI INTERCONNECT AND INTENTIONAL INDUCTOR IMPEDANCE EXTRACTION IN THE PRESENCE OF A MULTI-LAYER CONDUCTIVE SUBSTRATE

Patent #:	9377508	Issue Dt:	06/28/2016	Application #:	14257918	Filing Dt:	04/21/2014
Publication #:	US20140229779	Pub Dt:	08/14/2014
Title:	SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

Patent #:	9418195	Issue Dt:	08/16/2016	Application #:	14480247	Filing Dt:	09/08/2014
Publication #:	US20150067628	Pub Dt:	03/05/2015
Title:	LAYOUT CONTENT ANALYSIS FOR SOURCE MASK OPTIMIZATION ACCELERATION

Patent #:	9619600	Issue Dt:	04/11/2017	Application #:	14491834	Filing Dt:	09/19/2014
Publication #:	US20150149973	Pub Dt:	05/28/2015
Title:	THIRD PARTY COMPONENT DEBUGGING FOR INTEGRATED CIRCUIT DESIGN

Patent #:	9230054	Issue Dt:	01/05/2016	Application #:	14563285	Filing Dt:	12/08/2014
Publication #:	US20150161324	Pub Dt:	06/11/2015
Title:	HIGH-FREQUENCY VLSI INTERCONNECT AND INTENTIONAL INDUCTOR IMPEDANCE EXTRACTION IN THE PRESENCE OF A MULTI-LAYER CONDUCTIVE SUBSTRATE

Patent #:	9977080	Issue Dt:	05/22/2018	Application #:	14595021	Filing Dt:	01/12/2015
Publication #:	US20150226796	Pub Dt:	08/13/2015
Title:	GENERATING TEST SETS FOR DIAGNOSING SCAN CHAIN FAILURES

Patent #:	9734274	Issue Dt:	08/15/2017	Application #:	14610954	Filing Dt:	01/30/2015
Publication #:	US20150347633	Pub Dt:	12/03/2015
Title:	SYSTEM DESIGN MANAGEMENT

Patent #:	9720040	Issue Dt:	08/01/2017	Application #:	14803866	Filing Dt:	07/20/2015
Publication #:	US20150323600	Pub Dt:	11/12/2015
Title:	TIMING-AWARE TEST GENERATION AND FAULT SIMULATION

Patent #:	9664739	Issue Dt:	05/30/2017	Application #:	14853412	Filing Dt:	09/14/2015
Publication #:	US20160003907	Pub Dt:	01/07/2016
Title:	CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES

Patent #:	10228970	Issue Dt:	03/12/2019	Application #:	14949842	Filing Dt:	11/23/2015
Publication #:	US20160217006	Pub Dt:	07/28/2016
Title:	Domain Bounding For Symmetric Multiprocessing Systems

Patent #:	10210302	Issue Dt:	02/19/2019	Application #:	14987737	Filing Dt:	01/04/2016
Publication #:	US20160117437	Pub Dt:	04/28/2016
Title:	ELECTROSTATIC DAMAGE PROTECTION CIRCUITRY VERIFICATION

Patent #:	9684760	Issue Dt:	06/20/2017	Application #:	14993834	Filing Dt:	01/12/2016
Publication #:	US20160125122	Pub Dt:	05/05/2016
Title:	MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING

Patent #:	10089425	Issue Dt:	10/02/2018	Application #:	15014662	Filing Dt:	02/03/2016
Publication #:	US20160154916	Pub Dt:	06/02/2016
Title:	RESOURCE MAPPING IN A HARDWARE EMULATION ENVIRONMENT

Patent #:	9747397	Issue Dt:	08/29/2017	Application #:	15076991	Filing Dt:	03/22/2016
Publication #:	US20160203251	Pub Dt:	07/14/2016
Title:	MULTI-MODE MULTI-CORNER CLOCKTREE SYNTHESIS

Patent #:	10248028	Issue Dt:	04/02/2019	Application #:	15135339	Filing Dt:	04/21/2016
Publication #:	US20160238950	Pub Dt:	08/18/2016
Title:	SOURCE OPTIMIZATION FOR IMAGE FIDELITY AND THROUGHPUT

Patent #:	9714981	Issue Dt:	07/25/2017	Application #:	15150147	Filing Dt:	05/09/2016
Publication #:	US20160252573	Pub Dt:	09/01/2016
Title:	TEST-PER-CLOCK BASED ON DYNAMICALLY-PARTITIONED RECONFIGURABLE SCAN CHAINS

Patent #:	9703922	Issue Dt:	07/11/2017	Application #:	15174879	Filing Dt:	06/06/2016
Publication #:	US20160283645	Pub Dt:	09/29/2016
Title:	FRAGMENTATION POINT AND SIMULATION SITE ADJUSTMENT FOR RESOLUTION ENHANCEMENT TECHNIQUES

Patent #:	9874606	Issue Dt:	01/23/2018	Application #:	15188786	Filing Dt:	06/21/2016
Publication #:	US20170052227	Pub Dt:	02/23/2017
Title:	SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

Patent #:	10552565	Issue Dt:	02/04/2020	Application #:	15359595	Filing Dt:	11/22/2016
Publication #:	US20170147732	Pub Dt:	05/25/2017
Title:	Simultaneous Multi-Layer Fill Generation

Patent #:	10234506	Issue Dt:	03/19/2019	Application #:	15608716	Filing Dt:	05/30/2017
Publication #:	US20180017622	Pub Dt:	01/18/2018
Title:	CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES

Patent #:	10354044	Issue Dt:	07/16/2019	Application #:	15616729	Filing Dt:	06/07/2017
Publication #:	US20170270235	Pub Dt:	09/21/2017
Title:	FRAGMENTATION POINT AND SIMULATION SITE ADJUSTMENT FOR RESOLUTION ENHANCEMENT TECHNIQUES

Patent #:	10146897	Issue Dt:	12/04/2018	Application #:	15669827	Filing Dt:	08/04/2017
Title:	MULTI-MODE MULTI-CORNER CLOCKTREE SYNTHESIS

Patent #:	10657217	Issue Dt:	05/19/2020	Application #:	15792124	Filing Dt:	10/24/2017
Publication #:	US20180113970	Pub Dt:	04/26/2018
Title:	LATENCY TEST IN NETWORKING SYSTEM-ON-CHIP VERIFICATION

Patent #:	10664566	Issue Dt:	05/26/2020	Application #:	15792139	Filing Dt:	10/24/2017
Publication #:	US20180113961	Pub Dt:	04/26/2018
Title:	Bandwidth Test In Networking System-On-Chip Verification

Patent #:	10515168	Issue Dt:	12/24/2019	Application #:	15809892	Filing Dt:	11/10/2017
Title:	FORMAL VERIFICATION USING MICROTRANSACTIONS

Patent #:	10473721	Issue Dt:	11/12/2019	Application #:	15925655	Filing Dt:	03/19/2018
Title:	DATA STREAMING FOR TESTING IDENTICAL CIRCUIT BLOCKS

Patent #:	10775436	Issue Dt:	09/15/2020	Application #:	15925657	Filing Dt:	03/19/2018
Title:	STREAMING NETWORKS EFFICIENCY USING DATA THROTTLING

Patent #:	10929590	Issue Dt:	02/23/2021	Application #:	16217956	Filing Dt:	12/12/2018
Publication #:	US20190114384	Pub Dt:	04/18/2019
Title:	VERIFICATION OF PHOTONIC INTEGRATED CIRCUITS

Assignor

MENTOR GRAPHICS CORPORATION

Exec Dt:

12/30/2020

Newly Merged Entity Data

SIEMENS INDUSTRY SOFTWARE INC.

Exec Dt:

12/30/2020

Newly Merged Entity's New Name

SIEMENS INDUSTRY SOFTWARE INC.

5800 GRANITE PARKWAY, SUITE 600

PLANO, TEXAS 75024

Correspondence name and address
	SIEMENS CORPORATION IP DEPT - MAIL CODE INT-244
	3850 QUADRANGLE BOULEVARD
	ORLANDO, FL 32817

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