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Reel/Frame:037689/0719   Pages: 71
Recorded: 02/03/2016
Attorney Dkt #:35613/102
Conveyance: PATENT SECURITY AGREEMENT
Total properties: 704
Page 2 of 8
Pages: 1 2 3 4 5 6 7 8
1
Patent #:
Issue Dt:
04/22/2003
Application #:
09351406
Filing Dt:
07/09/1999
Title:
LINK AGGREGATION IN ETHERNET FRAME SWITCHES
2
Patent #:
Issue Dt:
09/17/2002
Application #:
09354426
Filing Dt:
07/16/1999
Title:
DUAL-DRIVE FAULT TOLERANT METHOD AND SYSTEM FOR ASSIGNING DATA CHUNKS TO COLUMN PARITY SETS
3
Patent #:
Issue Dt:
09/10/2002
Application #:
09375909
Filing Dt:
08/17/1999
Title:
SELF-HEALING COMPUTER SYSTEM STORAGE
4
Patent #:
Issue Dt:
05/25/2004
Application #:
09376773
Filing Dt:
08/17/1999
Title:
OBJECT ORIENTED FAULT TOLERANCE
5
Patent #:
Issue Dt:
02/25/2003
Application #:
09389954
Filing Dt:
09/03/1999
Title:
HOST-MEMORY BASED RAID SYSTEM, DEVICE, AND METHOD
6
Patent #:
Issue Dt:
08/20/2002
Application #:
09399981
Filing Dt:
09/20/1999
Title:
SUMS OF PRODUCTION DATAPATH
7
Patent #:
Issue Dt:
03/04/2003
Application #:
09439440
Filing Dt:
11/15/1999
Title:
SELF-HEALING COMPUTER SYSTEM STORAGE
8
Patent #:
Issue Dt:
11/05/2002
Application #:
09452618
Filing Dt:
12/01/1999
Title:
METHOD AND SYSTEM FOR NEGOTIATION OF THE HIGHEST COMMON LINK RATE AMONG NODES OF A FIBRE CHANNEL ARBITRATED LOOP
9
Patent #:
Issue Dt:
05/20/2003
Application #:
09455301
Filing Dt:
12/06/1999
Title:
METHOD OF CONSERVING MEMORY RESOURCES BY DIRECTLY DECOMPRESSING A COMPRESSED BIOS ASSOCIATED WITH AN OPTION ROM BIOS CHIP TO AN ALLOCATED CONVENTIONAL MEMORY OF SYSTEM MEMORY
10
Patent #:
Issue Dt:
12/23/2003
Application #:
09459972
Filing Dt:
12/14/1999
Title:
POS-PHY INTERFACE FOR INTERCONNECTION OF PHYSICAL LAYER DEVICES AND LINK LAYER DEVICES
11
Patent #:
Issue Dt:
04/01/2003
Application #:
09464127
Filing Dt:
12/16/1999
Title:
SYSTEM AND METHOD FOR PARITY CACHING BASED ON STRIPE LOCKING IN RAID DATA STORAGE
12
Patent #:
Issue Dt:
10/01/2002
Application #:
09464250
Filing Dt:
12/16/1999
Title:
SYSTEM AND METHOD FOR DATA STORAGE ARCHIVE BIT UPDATE AFTER SNAPSHOT BACKUP
13
Patent #:
Issue Dt:
01/21/2003
Application #:
09465057
Filing Dt:
12/16/1999
Title:
SYSTEM AND METHOD FOR ACCOMPLISHING DATA STORAGE MIGRATION BETWEEN RAID LEVELS
14
Patent #:
Issue Dt:
03/08/2005
Application #:
09465339
Filing Dt:
12/17/1999
Title:
F5-TO-F4 OAM ALARM NOTIFICATION AND CELL GENERATION IN MULTIPLE CONNECTION ATM SWITCHES
15
Patent #:
Issue Dt:
10/14/2003
Application #:
09471263
Filing Dt:
12/23/1999
Title:
MULTITHREADED ADDRESS RESOLUTION SYSTEM
16
Patent #:
Issue Dt:
06/24/2003
Application #:
09472153
Filing Dt:
12/27/1999
Title:
SCALEABLE BANDWIDTH INTERCONNECT FOR SIMULTANEOUS TRANSFER OF MIXED PLEISIOCHRONOUS DIGITAL HIERARCY (PDH) CLIENTS
17
Patent #:
Issue Dt:
09/14/2004
Application #:
09474945
Filing Dt:
12/30/1999
Title:
FIBRE CHANNEL INTERFACE CONTROLLER THAT PERFORMS NON-BLOCKING OUTPUT AND INPUT OF FIBRE CHANNEL DATA FRAMES AND ACKNOWLEDGEMENT FRAMES TO AND FROM A FIBRE CHANNEL
18
Patent #:
Issue Dt:
07/29/2003
Application #:
09475647
Filing Dt:
12/30/1999
Title:
COUNT/ADDRESS GENERATION CIRCUITRY
19
Patent #:
Issue Dt:
06/10/2003
Application #:
09475907
Filing Dt:
12/30/1999
Title:
METHOD AND SYSTEM FOR EFFICIENT I/O OPERATION COMPLETION IN A FIBRE CHANNEL NODE
20
Patent #:
Issue Dt:
02/25/2003
Application #:
09475908
Filing Dt:
12/30/1999
Title:
METHOD AND SYSTEM FOR EFFICIENT I/O OPERATION COMPLETION IN A FIBRE CHANNEL NODE USING AN APPLICATION SPECIFIC INTEGRATION CIRCUIT AND DETERMINING I/O OPERATION COMPLETION STATUS WITHIN AN INTERFACE CONTROLLER
21
Patent #:
Issue Dt:
08/10/2004
Application #:
09484248
Filing Dt:
01/18/2000
Publication #:
Pub Dt:
12/13/2001
Title:
DIGITAL DELAY LINE WITH SYNCHRONOUS CONTROL
22
Patent #:
Issue Dt:
04/02/2002
Application #:
09489917
Filing Dt:
01/24/2000
Title:
PAGE MEMORY MANAGEMENT IN NON TIME CRITICAL DATA BUFFERING APPLICATIONS
23
Patent #:
Issue Dt:
12/20/2005
Application #:
09494817
Filing Dt:
01/31/2000
Title:
METHOD AND SYSTEM INCREASING PERFORMANCE SUBSTITUTING FINITE STATE MACHINE CONTROL WITH HARDWARE-IMPLEMENTED DATA STRUCTURE MANIPULATION
24
Patent #:
Issue Dt:
11/06/2001
Application #:
09517702
Filing Dt:
03/02/2000
Title:
USE OF ANTIPHASE SIGNALS FOR PREDISTORTION TRAINING WITHIN AN AMPLIFIER SYSTEM
25
Patent #:
Issue Dt:
06/18/2002
Application #:
09523592
Filing Dt:
03/10/2000
Title:
MOS VARACTOR STRUCTURE WITH ENGINEERED VOLTAGE CONTROL RANGE
26
Patent #:
Issue Dt:
08/21/2001
Application #:
09531869
Filing Dt:
03/20/2000
Title:
Host adapter having paged payload buffers for simultaneously transferring data between a computer bus and a peripheral bus
27
Patent #:
Issue Dt:
02/27/2007
Application #:
09538132
Filing Dt:
03/29/2000
Title:
METHOD AND APPARATUS FOR PROGRAMMABLE LEXICAL PACKET CLASSIFIER
28
Patent #:
Issue Dt:
01/29/2002
Application #:
09548745
Filing Dt:
04/13/2000
Title:
High-speed, adaptive IDDQ measurement
29
Patent #:
Issue Dt:
05/11/2004
Application #:
09549878
Filing Dt:
04/17/2000
Title:
SHORT AND LONG TERM FAIR SHUFFLING FOR CROSSBAR SWITCH ARBITER
30
Patent #:
Issue Dt:
02/10/2004
Application #:
09552289
Filing Dt:
04/19/2000
Title:
INPUT/OUTPUT COMMUNICATION NETWORKS AND BOOTING PROTOCOLS
31
Patent #:
Issue Dt:
03/06/2007
Application #:
09557736
Filing Dt:
04/25/2000
Title:
METHOD AND APPARATUS FOR GRAMMATICAL PACKET CLASSIFIER
32
Patent #:
Issue Dt:
03/04/2003
Application #:
09564105
Filing Dt:
05/03/2000
Title:
INTELLIGENT EXPANSION ROM SHARING BUS SUBSYSTEM
33
Patent #:
Issue Dt:
10/07/2003
Application #:
09569593
Filing Dt:
05/09/2000
Title:
PARALLEL STRING PATTERN SEARCHES IN RESPECTIVE ONES OF ARRAY OF NANOCOMPUTERS
34
Patent #:
Issue Dt:
09/28/2004
Application #:
09574305
Filing Dt:
05/19/2000
Title:
METHOD AND APPARATUS FOR INTERCONNECTION OF FLOW-CONTROLLED COMMUNICATION
35
Patent #:
Issue Dt:
09/19/2006
Application #:
09580532
Filing Dt:
05/26/2000
Title:
METHOD AND APPARATUS FOR MANAGING DATA TRAFFIC BETWEEN A HIGH CAPACITY SOURCE AND MULTIPLE DESTINATIONS
36
Patent #:
Issue Dt:
08/19/2003
Application #:
09587538
Filing Dt:
06/01/2000
Title:
TWO-DIMENSIONAL EXECUTION QUEUE FOR HOST ADAPTERS
37
Patent #:
Issue Dt:
07/01/2003
Application #:
09595988
Filing Dt:
06/16/2000
Title:
DIGITAL PREDISTORTION METHODS FOR WIDEBAND AMPLIFIERS
38
Patent #:
Issue Dt:
09/28/2004
Application #:
09596142
Filing Dt:
06/16/2000
Title:
WIDEBAND DIGITAL PREDISTORTION LINEARIZER FOR NONLINEAR AMPLIFIERS
39
Patent #:
Issue Dt:
02/24/2004
Application #:
09596410
Filing Dt:
06/19/2000
Title:
TRANSMISSION ANTENNA ARRAY SYSTEM WITH PREDISTORTION
40
Patent #:
Issue Dt:
03/12/2002
Application #:
09596962
Filing Dt:
06/19/2000
Title:
Amplifier measurement and modeling processes for use in generating predistortion parameters
41
Patent #:
Issue Dt:
01/29/2002
Application #:
09597915
Filing Dt:
06/19/2000
Title:
Predistortion amplifier system with separately controllable amplifiers
42
Patent #:
Issue Dt:
01/28/2003
Application #:
09604203
Filing Dt:
06/27/2000
Title:
SYSTEM AND METHOD FOR DETECTING OF UNCHANGED PARITY DATA
43
Patent #:
Issue Dt:
07/23/2002
Application #:
09604347
Filing Dt:
06/27/2000
Title:
SYSTEM AND METHOD FOR ZEROING DATA STORAGE BLOCKS IN A RAID STORAGE IMPLEMENTATION
44
Patent #:
Issue Dt:
12/31/2002
Application #:
09604348
Filing Dt:
06/27/2000
Title:
SYSTEM AND METHOD FOR DETECTION OF DISK STORAGE BLOCKS CONTAINING UNIQUE VALUES
45
Patent #:
Issue Dt:
12/30/2003
Application #:
09608294
Filing Dt:
06/30/2000
Title:
BUS INTERFACE FOR CELL AND/OR PACKET DATA TRANSFER
46
Patent #:
Issue Dt:
02/26/2002
Application #:
09609912
Filing Dt:
07/03/2000
Title:
Programmable logic datapath that may be used in a field programmable device
47
Patent #:
Issue Dt:
07/27/2004
Application #:
09613174
Filing Dt:
07/10/2000
Title:
METHODS FOR ASSOCIATING END NODES ON A FABRIC
48
Patent #:
Issue Dt:
11/13/2001
Application #:
09617201
Filing Dt:
07/14/2000
Title:
Low charge-injection charge pump
49
Patent #:
Issue Dt:
05/20/2003
Application #:
09621964
Filing Dt:
07/21/2000
Title:
SWITCHED CAPACITOR TRANSMITTER PRE-DRIVER
50
Patent #:
Issue Dt:
11/16/2004
Application #:
09641980
Filing Dt:
08/21/2000
Title:
JITTER FREQUENCY SHIFTING DELTA-SIGMA MODULATED SIGNAL SYNCHRONIZATION MAPPER
51
Patent #:
Issue Dt:
04/06/2004
Application #:
09650774
Filing Dt:
08/29/2000
Title:
CONTENTION-BASED METHODS FOR GENERATING REDUCED NUMBER OF INTERRUPTS
52
Patent #:
Issue Dt:
10/09/2001
Application #:
09677034
Filing Dt:
09/29/2000
Title:
File array storage architecture having file system distributed across a data processing platform
53
Patent #:
Issue Dt:
08/31/2004
Application #:
09680834
Filing Dt:
10/06/2000
Title:
DUAL-CHANNEL SCSI CHIPS AND METHODS FOR CONFIGURING SEPARATE INTEROPERABILITY OF EACH CHANNEL OF THE SCSI CHIP
54
Patent #:
Issue Dt:
09/05/2006
Application #:
09687244
Filing Dt:
10/12/2000
Title:
METHOD AND APPARATUS FOR ESTABLISHING A PROFILE TABLE FOR HOST BUS ADAPTERS
55
Patent #:
Issue Dt:
09/05/2006
Application #:
09687699
Filing Dt:
10/12/2000
Title:
METHOD AND APPARATUS FOR DEVICE DISCOVERY
56
Patent #:
Issue Dt:
06/08/2004
Application #:
09690120
Filing Dt:
10/12/2000
Title:
METHOD AND APPARATUS FOR ADDRESS MAPPING
57
Patent #:
Issue Dt:
04/20/2004
Application #:
09691579
Filing Dt:
10/18/2000
Title:
CONTROLLER FAULT RECOVERY SYSTEM FOR A DISTRIBUTED FILE SYSTEM
58
Patent #:
Issue Dt:
06/01/2004
Application #:
09697119
Filing Dt:
10/27/2000
Title:
ADAPTIVE PHASE SHIFT FILTRATION OF POINTER JUSTIFICATION JITTER IN SYNCHRONOUS-PLESIOSYNCHRONOUS SIGNAL DESYNCHRONIZATION
59
Patent #:
Issue Dt:
05/28/2002
Application #:
09698356
Filing Dt:
10/27/2000
Title:
METHOD FOR SIGNALING IN A HIGH SPEED COMMUNICATION SYSTEM
60
Patent #:
Issue Dt:
09/03/2002
Application #:
09699075
Filing Dt:
10/27/2000
Title:
METHOD AND APPARATUS FOR HIGH-SPEED COMMUNICATION SYSTEM
61
Patent #:
Issue Dt:
04/20/2004
Application #:
09699255
Filing Dt:
10/27/2000
Title:
APPARATUS FOR A SWITCH ELEMENT IN A HIGH SPEED COMMUNICATION SYSTEM
62
Patent #:
Issue Dt:
02/05/2002
Application #:
09699260
Filing Dt:
10/27/2000
Title:
Method of for manipulating cells in a high speed communication system
63
Patent #:
Issue Dt:
07/27/2004
Application #:
09745034
Filing Dt:
12/20/2000
Title:
METHOD AND SYSTEM FOR FLOW CONTROL DURING THE DATA OUT PHASE OF THE PACKETIZED SCSI PROTOCOL
64
Patent #:
Issue Dt:
05/16/2006
Application #:
09745035
Filing Dt:
12/20/2000
Title:
METHOD AND STRUCTURE FOR SUPPORTING FLOW CONTROL BY A SCSI INITIATOR DURING THE DATA OUT PHASE OF THE PACKETIZED SCSI PROTOCOL
65
Patent #:
Issue Dt:
01/11/2005
Application #:
09745036
Filing Dt:
12/20/2000
Title:
METHOD AND STRUCTURE FOR SUPPORTING FLOW CONTROL BY A SCSI TARGET DURING THE DATA OUT PHASE OF THE PACKETIZED SCSI PROTOCOL
66
Patent #:
Issue Dt:
11/30/2004
Application #:
09745106
Filing Dt:
12/20/2000
Title:
METHOD AND STRUCTURE FOR SUPPORTING DATA STREAMING BY A SCSI INITIATOR DURING THE DATA IN PHASE OF THE PACKETIZED SCSI PROTOCOL
67
Patent #:
Issue Dt:
12/12/2006
Application #:
09752504
Filing Dt:
12/27/2000
Title:
METHODS FOR MANAGING HOST ADAPTER SETTINGS
68
Patent #:
Issue Dt:
07/06/2010
Application #:
09756680
Filing Dt:
01/10/2001
Publication #:
Pub Dt:
09/12/2002
Title:
SYSTEM INTERFACE FOR CELL AND/OR PACKET TRANSFER
69
Patent #:
Issue Dt:
12/06/2005
Application #:
09764680
Filing Dt:
01/18/2001
Title:
ADVANCED ADAPTIVE PRE-DISTORTION IN A RADIO FREQUENCY TRANSMITTER
70
Patent #:
Issue Dt:
04/05/2005
Application #:
09766602
Filing Dt:
01/23/2001
Publication #:
Pub Dt:
11/01/2001
Title:
BIPARTITE GRAPHICAL CONNECTION SCHEDULING IN TIME AND SPACE SWITCH FABRICS
71
Patent #:
Issue Dt:
07/27/2004
Application #:
09768859
Filing Dt:
01/23/2001
Title:
METHOD AND APPARATUS FOR INTELLIGENT FAILOVER IN A MULTI-PATH SYSTEM
72
Patent #:
Issue Dt:
11/23/2004
Application #:
09768860
Filing Dt:
01/23/2001
Title:
METHOD AND APPARATUS FOR A SEGREGATED INTERFACE FOR PARAMETER CONFIGURATION IN A MULTI-PATH FAILOVER SYSTEM
73
Patent #:
Issue Dt:
10/05/2004
Application #:
09768957
Filing Dt:
01/23/2001
Title:
INTELLIGENT LOAD BALANCING FOR A MULTI-PATH STORAGE SYSTEM
74
Patent #:
Issue Dt:
05/27/2003
Application #:
09770568
Filing Dt:
01/26/2001
Publication #:
Pub Dt:
12/27/2001
Title:
LOW NOISE WIDEBAND DIGITAL PREDISTORTION AMPLIFIER
75
Patent #:
Issue Dt:
09/06/2005
Application #:
09771144
Filing Dt:
01/26/2001
Title:
WIDEBAND ANALOG QUADRATURE MODULATOR/DEMODULATOR WITH PRE-COMPENSATION/POST-COMPENSATION CORRECTION
76
Patent #:
Issue Dt:
04/22/2003
Application #:
09775811
Filing Dt:
02/05/2001
Publication #:
Pub Dt:
08/08/2002
Title:
MULTI-CHANNEL CLOCK RECOVERY CIRCUIT
77
Patent #:
Issue Dt:
10/18/2005
Application #:
09789651
Filing Dt:
02/20/2001
Title:
CROSSBAR SUBSYSTEM AND METHOD
78
Patent #:
Issue Dt:
08/30/2005
Application #:
09790301
Filing Dt:
02/21/2001
Publication #:
Pub Dt:
08/22/2002
Title:
APPARATUS AND METHOD FOR DETERMINING BYTE GAIN AND LOSS ADJUSTMENTS IN A SONET/SDH NETWORK ELEMENT
79
Patent #:
Issue Dt:
11/09/2004
Application #:
09798100
Filing Dt:
03/02/2001
Title:
I/O SUBSYSTEM TOPOLOGY DISCOVERY METHOD
80
Patent #:
Issue Dt:
06/22/2004
Application #:
09798275
Filing Dt:
03/02/2001
Title:
AUTOMATIC ADDRESSING OF EXPANDERS IN I/O SUBSYSTEM
81
Patent #:
Issue Dt:
06/15/2004
Application #:
09798278
Filing Dt:
03/02/2001
Title:
METHODS FOR ASSIGNING ADDRESSES TO EXPANDED DEVICES IN I/O SUBSYSTEM
82
Patent #:
Issue Dt:
01/03/2006
Application #:
09840110
Filing Dt:
04/24/2001
Publication #:
Pub Dt:
02/21/2002
Title:
MULTI-CHANNEL SONET/SDH DESYNCHRONIZER
83
Patent #:
Issue Dt:
03/22/2005
Application #:
09845171
Filing Dt:
05/01/2001
Publication #:
Pub Dt:
01/03/2002
Title:
FLEXIBLE, SELF-ALIGNING TIME AND SPACE SWITCH FABRICS
84
Patent #:
Issue Dt:
06/08/2004
Application #:
09846875
Filing Dt:
05/01/2001
Title:
METHOD AND SYSTEM FOR ERROR CORRECTION OVER SERIAL LINK
85
Patent #:
Issue Dt:
09/20/2005
Application #:
09846975
Filing Dt:
05/01/2001
Title:
EXPANDER DEVICE FOR ISOLATING BUS SEGMENTS IN I/O SUBSYSTEM
86
Patent #:
Issue Dt:
04/10/2007
Application #:
09847076
Filing Dt:
05/01/2001
Publication #:
Pub Dt:
11/07/2002
Title:
NETWORK SWITCH PORT WITH WEIGHTED RANDOM EARLY DISCARD
87
Patent #:
Issue Dt:
06/06/2006
Application #:
09847077
Filing Dt:
05/01/2001
Publication #:
Pub Dt:
11/07/2002
Title:
NETWORK SWITCH PORT TRAFFIC MANAGER HAVING CONFIGURABLE PACKET AND CELL SERVICING
88
Patent #:
Issue Dt:
02/03/2004
Application #:
09847078
Filing Dt:
05/01/2001
Publication #:
Pub Dt:
11/21/2002
Title:
FAIR WEIGHTED QUEUING BANDWIDTH ALLOCATION SYSTEM FOR NETWORK SWITCH PORT
89
Patent #:
Issue Dt:
06/06/2006
Application #:
09847079
Filing Dt:
05/01/2001
Publication #:
Pub Dt:
10/28/2004
Title:
BACK PRESSURE CONTROL SYSTEM FOR NETWORK SWITCH PORT
90
Patent #:
Issue Dt:
07/18/2006
Application #:
09847711
Filing Dt:
05/01/2001
Title:
MULTISERVICE SWITCHING SYSTEM WITH DISTRIBUTED SWITCH FABRIC
91
Patent #:
Issue Dt:
06/22/2004
Application #:
09854075
Filing Dt:
05/10/2001
Publication #:
Pub Dt:
02/20/2003
Title:
FLEXIBLE FIFO SYSTEM FOR INTERFACING BETWEEN DATAPATHS OF VARIABLE LENGTH
92
Patent #:
Issue Dt:
03/01/2005
Application #:
09858321
Filing Dt:
05/15/2001
Title:
EXPANDER DEVICE AND METHOD FOR RESETTING BUS SEGMENTS IN I/O SUBSYSTEM SEGMENTED WITH EXPANDERS
93
Patent #:
Issue Dt:
02/28/2006
Application #:
09865258
Filing Dt:
05/25/2001
Publication #:
Pub Dt:
11/28/2002
Title:
METHOD AND APPARATUS FOR SCHEDULING STATIC AND DYNAMIC TRAFFIC THROUGH A SWITCH FABRIC
94
Patent #:
Issue Dt:
01/28/2003
Application #:
09866110
Filing Dt:
05/25/2001
Publication #:
Pub Dt:
11/28/2002
Title:
METHOD AND APPARATUS FOR SCALABLE ERROR CORRECTION CODE GENERATION PERFORMANCE
95
Patent #:
Issue Dt:
01/18/2005
Application #:
09872830
Filing Dt:
05/31/2001
Title:
METHOD AND SYSTEM FOR ACCESSING AN EXPANDED SCB ARRAY
96
Patent #:
Issue Dt:
09/28/2004
Application #:
09884270
Filing Dt:
06/19/2001
Publication #:
Pub Dt:
01/02/2003
Title:
SPARSE BYTE ENABLE INDICATOR FOR HIGH SPEED MEMORY ACCESS ARBITRATION METHOD AND APPARATUS
97
Patent #:
Issue Dt:
08/24/2004
Application #:
09891518
Filing Dt:
06/27/2001
Publication #:
Pub Dt:
03/20/2003
Title:
JITTER TOLERANCE IMPROVEMENT BY PHASE FILTRATION IN FEED-FORWARD DATA RECOVERY SYSTEMS
98
Patent #:
Issue Dt:
11/02/2004
Application #:
09898214
Filing Dt:
07/02/2001
Title:
METHOD AND APPARATUS FOR POST BOOT-UP DOMAIN VALIDATION
99
Patent #:
Issue Dt:
11/05/2002
Application #:
09899360
Filing Dt:
07/05/2001
Publication #:
Pub Dt:
01/24/2002
Title:
AMPLIFIER MEASUREMENT AND MODELING PROCESSES FOR USE IN GENERATING PREDISTORTION PARAMETERS
100
Patent #:
Issue Dt:
05/14/2002
Application #:
09899395
Filing Dt:
07/05/2001
Publication #:
Pub Dt:
04/18/2002
Title:
AMPLIFIER MEASUREMENT AND MODELING PROCESSES FOR USE IN GENERATING PREDISTORTION PARAMETERS
Assignors
1
Exec Dt:
01/15/2016
2
Exec Dt:
01/15/2016
Assignee
1
1585 BROADWAY
NEW YORK, NEW YORK 10036
Correspondence name and address
MARK LANGER
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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