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Reel/Frame:058793/0720   Pages: 4
Recorded: 11/03/2021
Attorney Dkt #:CONVERSANT TO MOSAID
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 24
1
Patent #:
6500754
Issue Dt:
12/31/2002
Application #:
09999661
Filing Dt:
10/31/2001
Title:
ANNEAL HILLOCK SUPPRESSION METHOD IN INTEGRATED CIRCUIT INTERCONNECTS
2
Patent #:
6462427
Issue Dt:
10/08/2002
Application #:
10024721
Filing Dt:
12/21/2001
Publication #:
US20020079591
Pub Dt:
06/27/2002
Title:
SEMICONDUCTOR CHIP, SET OF SEMICONDUCTOR CHIPS AND MULTICHIP MODULE
3
Patent #:
6794674
Issue Dt:
09/21/2004
Application #:
10084978
Filing Dt:
03/01/2002
Publication #:
US20020149116
Pub Dt:
10/17/2002
Title:
INTEGRATED CIRCUIT DEVICE AND METHOD FOR FORMING THE SAME
4
Patent #:
6646342
Issue Dt:
11/11/2003
Application #:
10097140
Filing Dt:
03/14/2002
Publication #:
US20020149034
Pub Dt:
10/17/2002
Title:
SEMICONDUCTOR CHIP AND MULTI-CHIP MODULE
5
Patent #:
6611029
Issue Dt:
08/26/2003
Application #:
10290158
Filing Dt:
11/08/2002
Title:
DOUBLE GATE SEMICONDUCTOR DEVICE HAVING SEPARATE GATES
6
Patent #:
6936480
Issue Dt:
08/30/2005
Application #:
10304573
Filing Dt:
11/26/2002
Publication #:
US20040023490
Pub Dt:
02/05/2004
Title:
METHOD OF CONTROLLING THE CHEMICAL MECHANICAL POLISHING OF STACKED LAYERS HAVING A SURFACE TOPOLOGY
7
Patent #:
7005358
Issue Dt:
02/28/2006
Application #:
10786401
Filing Dt:
02/25/2004
Publication #:
US20050026380
Pub Dt:
02/03/2005
Title:
TECHNIQUE FOR FORMING RECESSED SIDEWALL SPACERS FOR A POLYSILICON LINE
8
Patent #:
7155684
Issue Dt:
12/26/2006
Application #:
10879754
Filing Dt:
06/30/2004
Publication #:
US20040238850
Pub Dt:
12/02/2004
Title:
INTEGRATED CIRCUIT DEVICE AND METHOD FOR FORMING THE SAME
9
Patent #:
7091097
Issue Dt:
08/15/2006
Application #:
10933424
Filing Dt:
09/03/2004
Title:
END-OF-RANGE DEFECT MINIMIZATION IN SEMICONDUCTOR DEVICE
10
Patent #:
7259432
Issue Dt:
08/21/2007
Application #:
11068807
Filing Dt:
03/02/2005
Publication #:
US20050194637
Pub Dt:
09/08/2005
Title:
SEMICONDUCTOR DEVICE FOR REDUCING PARASITIC CAPACITANCE PRODUCED IN THE VICINITY OF A TRANSISTOR LOCATED WITHIN THE SEMICONDUCTOR DEVICE
11
Patent #:
7203085
Issue Dt:
04/10/2007
Application #:
11073738
Filing Dt:
03/08/2005
Publication #:
US20050201181
Pub Dt:
09/15/2005
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
12
Patent #:
7473623
Issue Dt:
01/06/2009
Application #:
11428022
Filing Dt:
06/30/2006
Publication #:
US20080003789
Pub Dt:
01/03/2008
Title:
PROVIDING STRESS UNIFORMITY IN A SEMICONDUCTOR DEVICE
13
Patent #:
7531403
Issue Dt:
05/12/2009
Application #:
11538001
Filing Dt:
10/02/2006
Publication #:
US20080079074
Pub Dt:
04/03/2008
Title:
SOI SEMICONDUCTOR COMPONENTS AND METHODS FOR THEIR FABRICATION
14
Patent #:
7465974
Issue Dt:
12/16/2008
Application #:
11633569
Filing Dt:
12/05/2006
Publication #:
US20070079261
Pub Dt:
04/05/2007
Title:
INTEGRATED CIRCUIT DEVICE AND METHOD FOR FORMING THE SAME
15
Patent #:
7504287
Issue Dt:
03/17/2009
Application #:
11689764
Filing Dt:
03/22/2007
Publication #:
US20080233738
Pub Dt:
09/25/2008
Title:
METHODS FOR FABRICATING AN INTEGRATED CIRCUIT
16
Patent #:
7754556
Issue Dt:
07/13/2010
Application #:
12027583
Filing Dt:
02/07/2008
Publication #:
US20090001484
Pub Dt:
01/01/2009
Title:
REDUCING TRANSISTOR JUNCTION CAPACITANCE BY RECESSING DRAIN AND SOURCE REGIONS
17
Patent #:
7816199
Issue Dt:
10/19/2010
Application #:
12037533
Filing Dt:
02/26/2008
Publication #:
US20090035924
Pub Dt:
02/05/2009
Title:
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING AN IMPLANTATION OF IONS OF A NON-DOPING ELEMENT
18
Patent #:
7737473
Issue Dt:
06/15/2010
Application #:
12271501
Filing Dt:
11/14/2008
Publication #:
US20090078968
Pub Dt:
03/26/2009
Title:
INTEGRATED CIRCUIT DEVICE AND METHOD FOR FORMING THE SAME
19
Patent #:
7986008
Issue Dt:
07/26/2011
Application #:
12413185
Filing Dt:
03/27/2009
Publication #:
US20090184372
Pub Dt:
07/23/2009
Title:
SOI SEMICONDUCTOR COMPONENTS AND METHODS FOR THEIR FABRICATION
20
Patent #:
8318598
Issue Dt:
11/27/2012
Application #:
12537321
Filing Dt:
08/07/2009
Publication #:
US20100078823
Pub Dt:
04/01/2010
Title:
CONTACTS AND VIAS OF A SEMICONDUCTOR DEVICE FORMED BY A HARD MASK AND DOUBLE EXPOSURE
21
Patent #:
8063417
Issue Dt:
11/22/2011
Application #:
12772604
Filing Dt:
05/03/2010
Publication #:
US20100244102
Pub Dt:
09/30/2010
Title:
INTEGRATED CIRCUIT DEVICE AND METHOD FOR FORMING THE SAME
22
Patent #:
8183605
Issue Dt:
05/22/2012
Application #:
12791290
Filing Dt:
06/01/2010
Publication #:
US20100237431
Pub Dt:
09/23/2010
Title:
REDUCING TRANSISTOR JUNCTION CAPACITANCE BY RECESSING DRAIN AND SOURCE REGIONS
23
Patent #:
9239979
Issue Dt:
01/19/2016
Application #:
14598219
Filing Dt:
01/15/2015
Title:
SYNTHETIC BARCODE PAYMENT SYSTEM AND METHOD
24
Patent #:
9489670
Issue Dt:
11/08/2016
Application #:
14836456
Filing Dt:
08/26/2015
Publication #:
US20160210613
Pub Dt:
07/21/2016
Title:
HYBRID WIRELESS SHORT RANGE PAYMENT SYSTEM AND METHOD
Assignor
1
CONVERSANT INTELLECTUAL PROPERTY INC.
Exec Dt:
04/01/2021
Assignee
1
MOSAID TECHNOLOGIES INCORPORATED
515 LEGGET DRIVE
SUITE 100
OTTAWA, CANADA K2K 3G4
Correspondence name and address
CONVERSANT IP MANAGEMENT CORP.
5830 GRANITE PARKWAY #100-247
SUITE 247
PLANO, TX 75024

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