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Patent Assignment Details

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Reel/Frame:	038768/0721			Pages:	6
		Recorded:	05/20/2016
Attorney Dkt #:	070852.000001
Conveyance:	CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).

Total properties: 11

Patent #:	NONE	Issue Dt:		Application #:	13328792	Filing Dt:	12/16/2011
Publication #:	US20130159667	Pub Dt:	06/20/2013
Title:	Vector Size Agnostic Single Instruction Multiple Data (SIMD) Processor Architecture

Patent #:	10534614	Issue Dt:	01/14/2020	Application #:	13491781	Filing Dt:	06/08/2012
Publication #:	US20130332703	Pub Dt:	12/12/2013
Title:	Rescheduling Threads Using Different Cores In A Multithreaded Microprocessor Having A Shared Register Pool

Patent #:	NONE	Issue Dt:		Application #:	13773818	Filing Dt:	02/22/2013
Publication #:	US20140244987	Pub Dt:	08/28/2014
Title:	Precision Exception Signaling for Multiple Data Architecture

Patent #:	NONE	Issue Dt:		Application #:	13774140	Filing Dt:	02/22/2013
Publication #:	US20140244977	Pub Dt:	08/28/2014
Title:	Deferred Saving of Registers in a Shared Register Pool for a Multithreaded Microprocessor

Patent #:	NONE	Issue Dt:		Application #:	13782600	Filing Dt:	03/01/2013
Publication #:	US20140250289	Pub Dt:	09/04/2014
Title:	Branch Target Buffer With Efficient Return Prediction Capability

Patent #:	NONE	Issue Dt:		Application #:	13789394	Filing Dt:	03/07/2013
Publication #:	US20140258667	Pub Dt:	09/11/2014
Title:	Apparatus and Method for Memory Operation Bonding

Patent #:	NONE	Issue Dt:		Application #:	13789427	Filing Dt:	03/07/2013
Publication #:	US20140258697	Pub Dt:	09/11/2014
Title:	SCHEDULING APPARATUS AND METHOD FOR WAKING UP INSTRUCTIONS BASED ON AN INSTRUCTION DEPENDENCY VECTOR AND AN INSTRUCTION PICKED VECTOR

Patent #:	10540179	Issue Dt:	01/21/2020	Application #:	13789467	Filing Dt:	03/07/2013
Publication #:	US20140258694	Pub Dt:	09/11/2014
Title:	Apparatus and Method for Bonding Branch Instruction with Architectural Delay Slot

Patent #:	9563476	Issue Dt:	02/07/2017	Application #:	14837109	Filing Dt:	08/27/2015
Publication #:	US20150370605	Pub Dt:	12/24/2015
Title:	Resource Sharing Using Process Delay

Assignor

Exec Dt:

03/10/2014

Assignee

3201 SCOTT BLVD

SANTA CLARA, CALIFORNIA 95054

Correspondence name and address
	VINCENT M DELUCA
	1909 K ST., NW
	NINTH FLOOR
	WASHINGTON, DC 20006

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