skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:024723/0724   Pages: 9
Recorded: 07/22/2010
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 32
1
Patent #:
Issue Dt:
01/03/1995
Application #:
08249306
Filing Dt:
05/24/1994
Title:
SELF-ALIGNED CONTACT PROCESS
2
Patent #:
Issue Dt:
01/16/1996
Application #:
08422291
Filing Dt:
04/14/1995
Title:
METHOD FOR FABRICATING A STACKED CAPACITOR FOR DYNAMIC RANDOM ACCESS MEMORY CELL
3
Patent #:
Issue Dt:
09/22/1998
Application #:
08740148
Filing Dt:
10/22/1996
Title:
SILICON ON INSULATOR (SOI) DRAM CELL STRUCTURE AND PROCESS
4
Patent #:
Issue Dt:
11/02/1999
Application #:
08775813
Filing Dt:
12/31/1996
Title:
METHOD FOR INCREASING CAPACITANCE
5
Patent #:
Issue Dt:
05/19/1998
Application #:
08790793
Filing Dt:
01/30/1997
Title:
METHOD FOR FABRICATING A STORAGE ELECTRODE WITHOUT POLYSILICON BRIDGE AND UNDERCUT
6
Patent #:
Issue Dt:
09/05/2000
Application #:
08996697
Filing Dt:
12/23/1997
Title:
METHOD OF FABRICATING A DYNAMIC RANDOM ACCESS MEMORY DEVICE
7
Patent #:
Issue Dt:
11/28/2000
Application #:
09008863
Filing Dt:
01/20/1998
Title:
METHOD OF FABRICATING A CAPACITOR OF A DYNAMIC RANDOM ACCESS MEMORY
8
Patent #:
Issue Dt:
11/06/2001
Application #:
09048637
Filing Dt:
03/26/1998
Title:
METHOD OF FIELD IMPLANTATION
9
Patent #:
Issue Dt:
11/28/2000
Application #:
09096349
Filing Dt:
06/12/1998
Title:
METHOD FOR INCREASING CAPACITANCE
10
Patent #:
Issue Dt:
05/29/2001
Application #:
09096351
Filing Dt:
06/12/1998
Title:
METHOD FOR INCREASING CAPACITANCE
11
Patent #:
Issue Dt:
12/07/1999
Application #:
09145711
Filing Dt:
09/02/1998
Title:
METHOD OF FABRICATING DRAM CAPACITOR
12
Patent #:
Issue Dt:
08/29/2000
Application #:
09164620
Filing Dt:
10/01/1998
Title:
METHOD FOR FABRICATING AN ELECTRODE STRUCTURE FOR A CYLINDRICAL CAPACITOR IN INTEGRATED CIRCUIT
13
Patent #:
Issue Dt:
10/31/2000
Application #:
09172407
Filing Dt:
10/14/1998
Title:
METHOD FOR FABRICATING A CYLINDER CAPACITOR
14
Patent #:
Issue Dt:
01/02/2001
Application #:
09181302
Filing Dt:
10/28/1998
Title:
METHOD OF FORMING CONTACT
15
Patent #:
Issue Dt:
05/30/2000
Application #:
09191677
Filing Dt:
11/13/1998
Title:
METHOD OF MANUFACTURING EMBEDDED DRAM
16
Patent #:
Issue Dt:
06/11/2002
Application #:
09208601
Filing Dt:
12/08/1998
Title:
METHOD FOR MANUFACUTRING LOWER ELECTRODE OF DRAM CAPACITOR
17
Patent #:
Issue Dt:
03/13/2001
Application #:
09208612
Filing Dt:
12/08/1998
Title:
METHOD OF FABRICATING SELF-ALIGNED CONTACT IN EMBEDDED DRAM
18
Patent #:
Issue Dt:
01/08/2002
Application #:
09237496
Filing Dt:
01/25/1999
Title:
METHOD FOR FABRICATING AN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY
19
Patent #:
Issue Dt:
12/05/2000
Application #:
09267883
Filing Dt:
03/11/1999
Title:
METHOD OF MANUFACTURING LINER INSULATING LAYER
20
Patent #:
Issue Dt:
11/21/2000
Application #:
09287881
Filing Dt:
04/07/1999
Title:
METHOD FOR FORMING GATE SPACERS WITH DIFFERENT WIDTH
21
Patent #:
Issue Dt:
09/18/2001
Application #:
09316979
Filing Dt:
05/24/1999
Title:
METHOD OF FABRICATING STORAGE NODE
22
Patent #:
Issue Dt:
07/30/2002
Application #:
09375518
Filing Dt:
08/17/1999
Title:
METHOD FOR FABRICATING AN EMBEDDED DRAM WITH SELF-ALIGNED BORDERLESS CONTACTS
23
Patent #:
Issue Dt:
08/21/2001
Application #:
09421261
Filing Dt:
10/20/1999
Title:
METHOD OF FORMING A NODE CONTACT HOLE ON A SEMICONDUCTOR WAFER
24
Patent #:
Issue Dt:
10/16/2001
Application #:
09422577
Filing Dt:
10/21/1999
Title:
METHOD FOR FABRICATING A BURIED BIT LINE IN A DRAM CELL
25
Patent #:
Issue Dt:
01/02/2001
Application #:
09431941
Filing Dt:
11/01/1999
Title:
METHOD FOR ENHANCING THE RELIABILITY OF A DIELECTRIC LAYER OF A SEMICONDUCTOR WAFER
26
Patent #:
Issue Dt:
08/21/2001
Application #:
09435047
Filing Dt:
11/08/1999
Title:
FABRICATION METHOD FOR A METAL OXIDE SEMICONDUCTOR HAVING A DOUBLE DIFFUSED DRAIN
27
Patent #:
Issue Dt:
02/20/2001
Application #:
09467590
Filing Dt:
12/20/1999
Title:
METHOD OF FABRICATING CAPACITOR
28
Patent #:
Issue Dt:
12/11/2001
Application #:
09493671
Filing Dt:
01/28/2000
Title:
Method of forming a lower storage node of a capacitor for dynamic random access memory
29
Patent #:
Issue Dt:
07/17/2001
Application #:
09497669
Filing Dt:
02/04/2000
Title:
Method of forming a self-aligned contact hole on a semiconductor wafer
30
Patent #:
Issue Dt:
08/13/2002
Application #:
09682402
Filing Dt:
08/30/2001
Title:
METHOD OF FORMING A LOWER STORAGE NODE OF A CAPACITOR
31
Patent #:
Issue Dt:
04/09/2002
Application #:
09774455
Filing Dt:
01/31/2001
Title:
Method for upgrading quality of dram capacitor and wafer-to-wafer uniformity
32
Patent #:
Issue Dt:
06/18/2002
Application #:
09799909
Filing Dt:
03/06/2001
Publication #:
Pub Dt:
06/20/2002
Title:
Fabrication method for an embedded dynamic random access memory (DRAM)
Assignor
1
Exec Dt:
05/20/2010
Assignee
1
2711 CENTERVILLE ROAD, SUITE 400
WILMINGTON, DELAWARE 19808
Correspondence name and address
AISAWA TECHNOLOGIES, LLC
2711 CENTERVILLE ROAD, SUITE 400
WILMINGTON, DE 19808

Search Results as of: 09/21/2024 09:29 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT