Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 008995/0725 | |
| Pages: | 5 |
| | Recorded: | 02/23/1998 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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11/19/1991
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Application #:
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06706142
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Filing Dt:
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02/27/1985
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Title:
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MULTIPROCESSOR COMPUTER SYSTEM EMPLOYING A PLURALITY OF TIGHTLY COUPLED PROCESSORS WITH INTERRUPT VECTOR BUS
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Patent #:
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Issue Dt:
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07/05/1988
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Application #:
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06749581
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Filing Dt:
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06/27/1985
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Title:
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HIERARCHICAL CACHE MEMORY SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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11/21/1995
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Application #:
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08252996
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Filing Dt:
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06/02/1994
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Title:
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LINEAR ACCELERATED DEVICE
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Patent #:
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Issue Dt:
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09/17/1996
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Application #:
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08443527
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Filing Dt:
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05/18/1995
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Title:
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LINEAR ACCELERATED DEVICE
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Assignee
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| 901 SAN ANTONIO ROAD |
| PALO ALTO, CALIFORNIA 94303 |
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Correspondence name and address
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EVENSON, MCKEOWN, EDWARDS, ET AL.
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GARY R. EDWARDS, ESQUIRE
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1200 G. STREET, N.W. SUITE 700
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WASHINGTON, D.C. 20005
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