Total properties:
62
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Patent #:
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Issue Dt:
|
05/30/2000
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Application #:
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09019244
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Filing Dt:
|
02/05/1998
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Title:
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METHOD AND APPARATUS FOR A N-NARY LOGIC CIRCUIT USING 1 OF N SIGNALS
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Patent #:
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Issue Dt:
|
06/28/2005
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Application #:
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09019278
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Filing Dt:
|
02/05/1998
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Title:
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METHOD AND APPARATUS FOR A 1 OF N SIGNAL
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Patent #:
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Issue Dt:
|
05/23/2000
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Application #:
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09019355
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Filing Dt:
|
02/05/1998
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Title:
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METHOD AND APPARATUS FOR AN N-NARY LOGIC CIRCUIT USING 1 OF 4 SIGNALS
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Patent #:
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Issue Dt:
|
03/13/2001
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Application #:
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09073478
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Filing Dt:
|
05/06/1998
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Title:
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METHOD AND APPARATUS FOR ROUTING 1 OF N SIGNALS
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Patent #:
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Issue Dt:
|
04/03/2001
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Application #:
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09073479
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Filing Dt:
|
05/06/1998
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Title:
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METHOD AND APPARATUS FOR ROUTING 1 OF 4 SIGNALS
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Patent #:
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|
Issue Dt:
|
01/09/2001
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Application #:
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09120771
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Filing Dt:
|
07/22/1998
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Title:
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A METHOD AND APPARATUS FOR SELECTING AN INTERMEDIATE RESULT FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
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Patent #:
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Issue Dt:
|
02/06/2001
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Application #:
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09120775
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Filing Dt:
|
07/22/1998
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Title:
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METHOD AND APPARATUS FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
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Patent #:
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Issue Dt:
|
11/21/2000
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Application #:
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09120776
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Filing Dt:
|
07/22/1998
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Title:
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METHOD AND APPARATUS FOR FORMATTING AN INTERMEDIATE RESULT FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
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Patent #:
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Issue Dt:
|
01/16/2001
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Application #:
|
09120814
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Filing Dt:
|
07/22/1998
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Title:
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SHIFTING FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
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|
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Patent #:
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|
Issue Dt:
|
03/27/2001
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Application #:
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09122504
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Filing Dt:
|
07/24/1998
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Title:
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METHOD AND APPARATUS FOR TW0-STAGE ADDRESS GENERATION
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|
|
Patent #:
|
|
Issue Dt:
|
06/11/2002
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Application #:
|
09123742
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Filing Dt:
|
07/28/1998
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Title:
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METHOD AND APPARATUS FOR LOGIC CIRCUIT TRANSITION DETECTION
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Patent #:
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Issue Dt:
|
07/11/2000
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Application #:
|
09124207
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Filing Dt:
|
07/28/1998
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Title:
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METHOD AND APPARATUS FOR LOGIC CIRCUIT SPEED DETECTION
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|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
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Application #:
|
09150162
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Filing Dt:
|
09/09/1998
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Title:
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METHOD AND APPARATUS FOR A RAM CIRCUIT HAVING N-NARY WORD LINE GENERATION
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|
|
Patent #:
|
|
Issue Dt:
|
04/04/2000
|
Application #:
|
09150258
|
Filing Dt:
|
09/09/1998
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Title:
|
METHOD AND APPARATUS FOR A RAM CIRCUIT HAVING N-NARY OUTPUT INTERFACE
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|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
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Application #:
|
09150389
|
Filing Dt:
|
09/09/1998
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Title:
|
METHOD AND APPARATUS FOR AN ADDRESS TRIGGERED RAM CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
09150575
|
Filing Dt:
|
09/10/1998
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Title:
|
METHOD AND APPARATUS FOR AN N-NARY HPG GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09150717
|
Filing Dt:
|
09/10/1998
|
Title:
|
METHOD AND APPARATUS FOR AN N-NARY SUM/HPG ADDER/SUBTRACTOR GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09150720
|
Filing Dt:
|
09/10/1998
|
Title:
|
METHOD AND APPARATUS FOR AN N-NARY SUM/HPG GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09150829
|
Filing Dt:
|
09/10/1998
|
Title:
|
METHOD AND APPARATUS FOR AN N-NARY ADDER GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
09179330
|
Filing Dt:
|
10/27/1998
|
Title:
|
METHOD AND APPARATUS FOR LOGIC SYNCHRONIZATION
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|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09179626
|
Filing Dt:
|
10/27/1998
|
Title:
|
METHOD AND APPARATUS THAT ALLOWS THE LOGIC STATE OF A LOGIC GATE TO BE TESTED WHEN STOPPING OR STARTING THE LOGIC GATE'S CLOCK
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09179745
|
Filing Dt:
|
10/27/1998
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Title:
|
METHOD AND APPARATUS FOR GENERATING CLOCK SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09181405
|
Filing Dt:
|
10/28/1998
|
Title:
|
METHOD AND APPARATUS FOR AN ENHANCED FLOATING POINT UNIT WITH GRAPHICS AND INTEGER CAPABILITIES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
09181406
|
Filing Dt:
|
10/28/1998
|
Title:
|
METHOD AND APPARATUS FOR A LATE PIPELINE ENHANCED FLOATING POINT UNIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09191813
|
Filing Dt:
|
11/13/1998
|
Title:
|
METHOD AND APPARATUS FOR BUILT-IN SELF-TEST OF LOGIC CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2001
|
Application #:
|
09195024
|
Filing Dt:
|
11/18/1998
|
Title:
|
METHOD AND APPARATUS FOR SATURATION IN AN N-NARY ADDER/SUBTRACTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09195751
|
Filing Dt:
|
11/18/1998
|
Title:
|
METHOD AND APPARATUS FOR INTERRUPTION OF CARRY PROPAGATION ON PARTITION BOUNDARIES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2001
|
Application #:
|
09195752
|
Filing Dt:
|
11/18/1998
|
Title:
|
METHOD AND APPARATUS FOR DYNAMIC PARTITIONABLE SATURATING ADDER/SUBTRACTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2001
|
Application #:
|
09195757
|
Filing Dt:
|
11/18/1998
|
Title:
|
METHOD AND APPARATUS FOR HANDLING PARTIAL REGISTER ACCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09195758
|
Filing Dt:
|
11/18/1998
|
Title:
|
METHOD AND APPARATUS THAT ENFORCES A REGIONAL MEMORY MODEL IN HIERARCHICAL MEMORY SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09195779
|
Filing Dt:
|
11/18/1998
|
Title:
|
METHOD AND APPARATUS FOR TLB MEMORY ORDERING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09198843
|
Filing Dt:
|
11/24/1998
|
Title:
|
OSCILLATING AIR JETS FOR REDUCING HSI NOISE 01
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2001
|
Application #:
|
09206463
|
Filing Dt:
|
12/07/1998
|
Title:
|
METHOD AND APPARATUS FOR 3-STAGE 32-BIT ADDER/SUBSTRACTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2001
|
Application #:
|
09206539
|
Filing Dt:
|
12/07/1998
|
Title:
|
METHOD AND APPARATUS FOR A 1 OF 4 SHIFTER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09206631
|
Filing Dt:
|
12/07/1998
|
Title:
|
METHOD AND APPARATUS FOR AN N-NARY EQUALITY COMPARATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2002
|
Application #:
|
09206830
|
Filing Dt:
|
12/07/1998
|
Title:
|
METHOD AND APPARATUS FOR N-NARY INCREMENTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2001
|
Application #:
|
09206900
|
Filing Dt:
|
12/07/1998
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Title:
|
METHOD AND APPARATUS FOR TRANSFORMING PSEUDORANDOM BINARY TEST PATTERNS INTO TEST STIMULUS PATTERNS APPROPRIATE FOR CIRCUITS HAVING 1 OF N ENCODED INPUTS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09206905
|
Filing Dt:
|
12/07/1998
|
Title:
|
METHOD AND APPARATUS FOR TRANSFORMING PSEUDORANDOM BINARY PATTERNS INTO TEST STIMULUS PATTERNS APPROPRIATE FOR CIRCUITS HAVING 1 OF N ENCODED INPUTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09206906
|
Filing Dt:
|
12/07/1998
|
Title:
|
METHOD AND APPARATUS FOR AN N-NARY MAGNITUDE COMPARATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09207806
|
Filing Dt:
|
12/09/1998
|
Title:
|
METHOD AND APPARATUS FOR 1 OF 4 REGISTER FILE DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09209207
|
Filing Dt:
|
12/10/1998
|
Title:
|
A METHOD AND APPARATUS FOR A LOGIC CIRCUIT WITH CONSTANT POWER CONSUMPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2001
|
Application #:
|
09209935
|
Filing Dt:
|
12/11/1998
|
Title:
|
DYNAMIC 3-LEVEL PARTIAL RESULT MERGE ADDER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
09209967
|
Filing Dt:
|
12/10/1998
|
Title:
|
METHOD AND APPARATUS FOR A N-NARY LOGIC CIRCUIT USING CAPACITANCE ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2002
|
Application #:
|
09210024
|
Filing Dt:
|
12/11/1998
|
Title:
|
METHOD AND APPARATUS FOR A LOGIC CIRCUIT DESIGN TOOL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09210408
|
Filing Dt:
|
12/11/1998
|
Title:
|
METHOD AND APPARATUS FOR N-NARY HARDWARE DESCRIPTION LANGUAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09210410
|
Filing Dt:
|
12/11/1998
|
Title:
|
METHOD AND APPARATUS FOR N-NARY LOGIC CIRCUIT DESIGN TOOL WITH PRECHARGE CIRCUIT EVALUATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
09291659
|
Filing Dt:
|
04/14/1999
|
Title:
|
METHOD AND APPARATUS FOR MULTI-BIT REGISTER CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09373516
|
Filing Dt:
|
08/12/1999
|
Title:
|
METHOD AND APPARATUS THAT SUPPORTS MULTIPLE ASSIGNMENT CODE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
|
09373840
|
Filing Dt:
|
08/13/1999
|
Title:
|
SOFTWARE SYSTEM BUILD METHOD AND APPARATUS THAT SUPPORTS MULTIPLE USERS IN A SOFTWARE DEVELOPMENT ENVIRONMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09374588
|
Filing Dt:
|
08/13/1999
|
Title:
|
METHOD AND APPARATUS FOR OBJECT CACHE REGISTRATION AND MAINTENANCE IN A NETWORKED SOFTWARE DEVELOPMENT ENVIRONMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2003
|
Application #:
|
09405474
|
Filing Dt:
|
09/24/1999
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Title:
|
MULTIPLE-STATE SIMULATION FOR NON-BINARY LOGIC
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
09405618
|
Filing Dt:
|
09/24/1999
|
Title:
|
SOFTWARE MODELING OF LOGIC SIGNALS CAPABLE OF HOLDING MORE THAN TWO VALUES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2003
|
Application #:
|
09406016
|
Filing Dt:
|
09/24/1999
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Title:
|
METHOD AND APPARATUS THAT REPORTS MULTIPLE STATUS EVENTS WITH A SINGLE MONITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
09406017
|
Filing Dt:
|
09/24/1999
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Title:
|
METHOD AND APPARATUS FOR A MONITOR THAT DETECTS AND REPORTS A STATUS EVENT TO A DATABASE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09458763
|
Filing Dt:
|
12/10/1999
|
Title:
|
METHOD AND APPARATUS FOR AN N-NARY LOGIC CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09458766
|
Filing Dt:
|
12/10/1999
|
Title:
|
METHOD AND APPARATUS FOR A RAM CIRCUIT HAVING N-NARY OUTPUT INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2002
|
Application #:
|
09468759
|
Filing Dt:
|
12/21/1999
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Title:
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METHOD AND APPARATUS FOR SCAN OF SYNCHRONIZED DYNAMIC LOGIC USING EMBEDDED SCAN GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09468760
|
Filing Dt:
|
12/21/1999
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Title:
|
METHOD AND APPARATUS FOR A SPECIAL STRESS MODE FOR N-NARY LOGIC THAT INITIALIZES THE LOGIC INTO A FUNCTIONALLY ILLEGAL STATE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09468972
|
Filing Dt:
|
12/21/1999
|
Title:
|
DYNAMIC LOGIC SCAN GATE METHOD AND APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2003
|
Application #:
|
09496008
|
Filing Dt:
|
02/01/2000
|
Title:
|
METHOD AND APPARATUS FOR PRE-BRANCH INSTRUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2002
|
Application #:
|
09503397
|
Filing Dt:
|
02/14/2000
|
Title:
|
Dynamic adjustment of the clock rate in logic circuits
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|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09527653
|
Filing Dt:
|
03/17/2000
|
Title:
|
ROUNDING ANTICIPATOR FOR FLOATING POINT OPERATIONS
|
|