Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 015428/0735 | |
| Pages: | 7 |
| | Recorded: | 12/08/2004 | | |
Conveyance: | CORRECTIVE COVERSHEET TO CORRECT SERIAL NUMBER PREVIOUSLY RECORDED ON REEL 015409, FRAME 0602. |
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Total properties:
4
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Patent #:
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Issue Dt:
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02/23/1999
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Application #:
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08857167
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Filing Dt:
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05/15/1997
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT ARRANGEMENT FABRICATION METHOD
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Patent #:
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Issue Dt:
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10/05/1999
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Application #:
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09188371
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Filing Dt:
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11/10/1998
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT ARRANGEMENT FABRICATION METHOD
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09339041
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Filing Dt:
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06/23/1999
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT ARRANGEMENT FABRICATION METHOD
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09564754
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Filing Dt:
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05/04/2000
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Title:
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Semiconductor integrated circuit arrangement fabrication method
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Assignee
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4-1, MARUNOUCHI 2-CHOME |
CHIYODA-KU, TOKYO, JAPAN |
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Correspondence name and address
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MATTINGLY, STANGER & MALUR, P.C.
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JOHN R. MATTINGLY
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1800 DIAGONAL ROAD, SUITE 370
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ALEXANDRIA, VA 22314
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