Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 012981/0737 | |
| Pages: | 3 |
| | Recorded: | 06/04/2002 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
10163208
|
Filing Dt:
|
06/04/2002
|
|
Title:
|
METHOD AND SYSTEM FOR CHECKING FOR POWER ERRORS IN ASIC DESIGNS
|
|
|
Assignee
|
|
|
|
|
| 1551 MCCARTHY BOULEVARD |
| MILPITAS, CALIFORNIA 95035 |
|
|
Correspondence name and address
|
| |
LSI LOGIC CORPORATION
|
| |
SANDEEP JAGGI
|
| |
1551 MCCARTHY BOULEVARD
|
| |
MILPITAS, CALIFORNIA 95035
|
Search Results as of:
05/28/2024 02:02 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
