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Reel/Frame:	046319/0743			Pages:	26
		Recorded:	06/07/2018
Attorney Dkt #:	327135-213
Conveyance:	SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 153
Page 2 of 2
Pages: 1 2

Patent #:	9755983	Issue Dt:	09/05/2017	Application #:	14521435	Filing Dt:	10/22/2014
Title:	MINIPACKET FLOW CONTROL

Patent #:	9940097	Issue Dt:	04/10/2018	Application #:	14527550	Filing Dt:	10/29/2014
Title:	REGISTERED FIFO

Patent #:	9990307	Issue Dt:	06/05/2018	Application #:	14527642	Filing Dt:	10/29/2014
Title:	SPLIT PACKET TRANSMISSION DMA ENGINE

Patent #:	9804959	Issue Dt:	10/31/2017	Application #:	14530599	Filing Dt:	10/31/2014
Publication #:	US20160124772	Pub Dt:	05/05/2016
Title:	In-Flight Packet Processing

Patent #:	9727512	Issue Dt:	08/08/2017	Application #:	14530758	Filing Dt:	11/02/2014
Title:	IDENTICAL PACKET MULTICAST PACKET READY COMMAND

Patent #:	9588928	Issue Dt:	03/07/2017	Application #:	14530759	Filing Dt:	11/02/2014
Title:	UNIQUE PACKET MULTICAST PACKET READY COMMAND

Patent #:	9727513	Issue Dt:	08/08/2017	Application #:	14530760	Filing Dt:	11/02/2014
Title:	UNICAST PACKET READY COMMAND

Patent #:	9887918	Issue Dt:	02/06/2018	Application #:	14530762	Filing Dt:	11/02/2014
Title:	Intelligent Packet Data Register File That Stalls Picoengine And Retrieves Data From A Larger Buffer

Patent #:	9417916	Issue Dt:	08/16/2016	Application #:	14530763	Filing Dt:	11/02/2014
Title:	Intelligent Packet Data Register File That Prefetches Data For Future Instruction Execution

Patent #:	9519484	Issue Dt:	12/13/2016	Application #:	14530764	Filing Dt:	11/02/2014
Title:	Picoengine Instruction That Controls An Intelligent Packet Data Register File Prefetch Function

Patent #:	9612841	Issue Dt:	04/04/2017	Application #:	14530765	Filing Dt:	11/02/2014
Title:	SLICE-BASED INTELLIGENT PACKET DATA REGISTER FILE

Patent #:	9385957	Issue Dt:	07/05/2016	Application #:	14537514	Filing Dt:	11/10/2014
Title:	FLOW KEY LOOKUP INVOLVING MULTIPLE SIMULTANEOUS CAM OPERATIONS TO IDENTIFY HASH VALUES IN A HASH BUCKET

Patent #:	9331906	Issue Dt:	05/03/2016	Application #:	14551057	Filing Dt:	11/23/2014
Title:	COMPARTMENTALIZATION OF THE USER NETWORK INTERFACE TO A DEVICE

Patent #:	9899996	Issue Dt:	02/20/2018	Application #:	14556135	Filing Dt:	11/29/2014
Title:	RECURSIVE LOOKUP WITH A HARDWARE TRIE STRUCTURE THAT HAS NO SEQUENTIAL LOGIC ELEMENTS

Patent #:	9330041	Issue Dt:	05/03/2016	Application #:	14556147	Filing Dt:	11/29/2014
Title:	STAGGERED ISLAND STRUCTURE IN AN ISLAND-BASED NETWORK FLOW PROCESSOR

Patent #:	9401880	Issue Dt:	07/26/2016	Application #:	14588084	Filing Dt:	12/31/2014
Title:	Flow Control Using A Local Event Ring In An Island-Based Network Flow Processor

Patent #:	9389908	Issue Dt:	07/12/2016	Application #:	14588280	Filing Dt:	12/31/2014
Title:	TRANSACTIONAL MEMORY THAT PERFORMS A TCAM 32-BIT LOOKUP OPERATION

Patent #:	9311004	Issue Dt:	04/12/2016	Application #:	14588342	Filing Dt:	12/31/2014
Title:	TRANSACTIONAL MEMORY THAT PERFORMS A PMM 32-BIT LOOKUP OPERATION

Patent #:	9703739	Issue Dt:	07/11/2017	Application #:	14590920	Filing Dt:	01/06/2015
Publication #:	US20160055112	Pub Dt:	02/25/2016
Title:	RETURN AVAILABLE PPI CREDITS COMMAND

Patent #:	9665519	Issue Dt:	05/30/2017	Application #:	14591003	Filing Dt:	01/07/2015
Publication #:	US20160055111	Pub Dt:	02/25/2016
Title:	USING A CREDITS AVAILABLE VALUE IN DETERMINING WHETHER TO ISSUE A PPI ALLOCATION REQUEST TO A PACKET ENGINE

Patent #:	9537801	Issue Dt:	01/03/2017	Application #:	14611224	Filing Dt:	01/31/2015
Title:	Distributed Packet Ordering System Having Separate Worker And Output Processors

Patent #:	9641448	Issue Dt:	05/02/2017	Application #:	14611231	Filing Dt:	01/31/2015
Title:	PACKET ORDERING SYSTEM USING AN ATOMIC TICKET RELEASE COMMAND OF A TRANSACTIONAL MEMORY

Patent #:	9348778	Issue Dt:	05/24/2016	Application #:	14631748	Filing Dt:	02/25/2015
Publication #:	US20150169479	Pub Dt:	06/18/2015
Title:	TRANSACTIONAL MEMORY THAT PERFORMS AN ALUT 32-BIT LOOKUP OPERATION

Patent #:	9304706	Issue Dt:	04/05/2016	Application #:	14631784	Filing Dt:	02/25/2015
Publication #:	US20150309755	Pub Dt:	10/29/2015
Title:	EFFICIENT COMPLEX NETWORK TRAFFIC MANAGEMENT IN A NON-UNIFORM MEMORY SYSTEM

Patent #:	9280297	Issue Dt:	03/08/2016	Application #:	14631804	Filing Dt:	02/25/2015
Title:	TRANSACTIONAL MEMORY THAT SUPPORTS A PUT WITH LOW PRIORITY RING COMMAND

Patent #:	9699084	Issue Dt:	07/04/2017	Application #:	14634847	Filing Dt:	03/01/2015
Title:	FORWARDING MESSAGES WITHIN A SWITCH FABRIC OF AN SDN SWITCH

Patent #:	9729442	Issue Dt:	08/08/2017	Application #:	14634848	Filing Dt:	03/01/2015
Title:	METHOD OF DETECTING LARGE FLOWS WITHIN A SWITCH FABRIC OF AN SDN SWITCH

Patent #:	9467378	Issue Dt:	10/11/2016	Application #:	14634849	Filing Dt:	03/01/2015
Title:	METHOD OF GENERATING SUBFLOW ENTRIES IN AN SDN SWITCH

Patent #:	9503372	Issue Dt:	11/22/2016	Application #:	14634851	Filing Dt:	03/01/2015
Title:	SDN PROTOCOL MESSAGE HANDLING WITHIN A MODULAR AND PARTITIONED SDN SWITCH

Patent #:	9678738	Issue Dt:	06/13/2017	Application #:	14671951	Filing Dt:	03/27/2015
Title:	SOFTWARE UPDATE METHODOLOGY

Patent #:	9900090	Issue Dt:	02/20/2018	Application #:	14690362	Filing Dt:	04/17/2015
Title:	INTER-PACKET INTERVAL PREDICTION LEARNING ALGORITHM

Patent #:	9971720	Issue Dt:	05/15/2018	Application #:	14724820	Filing Dt:	05/29/2015
Title:	DISTRIBUTED CREDIT FIFO LINK OF A CONFIGURABLE MESH DATA BUS

Patent #:	9176905	Issue Dt:	11/03/2015	Application #:	14724824	Filing Dt:	05/29/2015
Title:	RECURSIVE USE OF MULTIPLE HARDWARE LOOKUP STRUCTURES IN A TRANSACTIONAL MEMORY

Patent #:	9298495	Issue Dt:	03/29/2016	Application #:	14724826	Filing Dt:	05/29/2015
Title:	TRANSACTIONAL MEMORY THAT PERFORMS AN ATOMIC METERING COMMAND

Patent #:	9678866	Issue Dt:	06/13/2017	Application #:	14724827	Filing Dt:	05/29/2015
Title:	TRANSACTIONAL MEMORY THAT SUPPORTS PUT AND GET RING COMMANDS

Patent #:	9912591	Issue Dt:	03/06/2018	Application #:	14726421	Filing Dt:	05/29/2015
Title:	Flow Switch IC that Uses Flow IDs and an Exact-match Flow Table

Patent #:	9756152	Issue Dt:	09/05/2017	Application #:	14726423	Filing Dt:	05/29/2015
Title:	Making A Flow ID For An Exact-match Flow Table Using A Byte-Wide Multiplexer Circuit

Patent #:	9819585	Issue Dt:	11/14/2017	Application #:	14726428	Filing Dt:	05/29/2015
Title:	Making A Flow ID For An Exact-match Flow Table Using A Programmable Reduce Table Circuit

Patent #:	9807006	Issue Dt:	10/31/2017	Application #:	14726433	Filing Dt:	05/29/2015
Title:	Crossbar And An Egress Packet Modifier In An Exact-match Flow Switch

Patent #:	9641436	Issue Dt:	05/02/2017	Application #:	14726441	Filing Dt:	05/29/2015
Title:	GENERATING A FLOW ID BY PASSING PACKET DATA SERIALLY THROUGH TWO CCT CIRCUITS

Patent #:	9912533	Issue Dt:	03/06/2018	Application #:	14731370	Filing Dt:	06/04/2015
Title:	SERDES CHANNEL OPTIMIZATION

Patent #:	9854072	Issue Dt:	12/26/2017	Application #:	14818070	Filing Dt:	08/04/2015
Title:	Script-Controlled Egress Packet Modifier

Patent #:	9804976	Issue Dt:	10/31/2017	Application #:	14841300	Filing Dt:	08/31/2015
Title:	TRANSACTIONAL MEMORY THAT PERFORMS AN ATOMIC LOOK-UP, ADD AND LOCK OPERATION

Patent #:	9929933	Issue Dt:	03/27/2018	Application #:	14841717	Filing Dt:	09/01/2015
Title:	LOADING A FLOW TABLE WITH NEURAL NETWORK DETERMINED INFORMATION

Patent #:	9755948	Issue Dt:	09/05/2017	Application #:	14841723	Filing Dt:	09/01/2015
Title:	CONTROLLING AN OPTICAL BYPASS SWITCH IN A DATA CENTER BASED ON A NEURAL NETWORK OUTPUT RESULT

Patent #:	9727673	Issue Dt:	08/08/2017	Application #:	14885978	Filing Dt:	10/16/2015
Title:	SIMULTANEOUS SIMULATION OF MULTIPLE BLOCKS USING EFFICIENT PACKET COMMUNICATION TO EMULATE INTER-BLOCK BUSES

Patent #:	9755910	Issue Dt:	09/05/2017	Application #:	14923457	Filing Dt:	10/27/2015
Title:	MAINTAINING BYPASS PACKET COUNT VALUES

Patent #:	9755911	Issue Dt:	09/05/2017	Application #:	14923458	Filing Dt:	10/27/2015
Title:	ON-DEMAND GENERATION OF SYSTEM ENTRY PACKET COUNTS

Patent #:	9866480	Issue Dt:	01/09/2018	Application #:	14927455	Filing Dt:	10/29/2015
Title:	Hash Range Lookup Command

Patent #:	9891985	Issue Dt:	02/13/2018	Application #:	14929275	Filing Dt:	10/31/2015
Title:	256-Bit Parallel Parser And Checksum Circuit With 1-Hot State Information Bus

Patent #:	9891898	Issue Dt:	02/13/2018	Application #:	15173653	Filing Dt:	06/04/2016
Title:	LOW-LEVEL PROGRAMMING LANGUAGE PLUGIN TO AUGMENT HIGH-LEVEL PROGRAMMING LANGUAGE SETUP OF AN SDN SWITCH

Patent #:	10031878	Issue Dt:	07/24/2018	Application #:	15463857	Filing Dt:	03/20/2017
Publication #:	US20170192926	Pub Dt:	07/06/2017
Title:	Configurable Mesh Data Bus In An Island-Based Network Flow Processor

Patent #:	10228968	Issue Dt:	03/12/2019	Application #:	15688937	Filing Dt:	08/29/2017
Publication #:	US20170357594	Pub Dt:	12/14/2017
Title:	NETWORK INTERFACE DEVICE THAT ALERTS A MONITORING PROCESSOR IF CONFIGURATION OF A VIRTUAL NID IS CHANGED

Assignor

NETRONOME SYSTEMS, INC.

Exec Dt:

06/05/2018

Assignee

KREOS CAPITAL V (UK) LIMITED

25 OLD BURLINGTON STREET

LONDON, UNITED KINGDOM W1S 3AN

Correspondence name and address
	COOLEY LLP
	101 CALIFORNIA STREET, 5TH FLOOR
	SAN FRANCISCO, CA 94111

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