Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 016026/0756 | |
| Pages: | 10 |
| | Recorded: | 04/07/2005 | | |
| Conveyance: | TRANSLATION CERTIFICATE |
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Total properties:
6
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Patent #:
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Issue Dt:
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02/08/2005
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Application #:
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10627277
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Filing Dt:
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07/25/2003
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Publication #:
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Pub Dt:
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01/29/2004
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Title:
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METHOD FOR FABRICATING MOS TRANSISTORS
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Patent #:
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Issue Dt:
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02/08/2005
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Application #:
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10627277
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Filing Dt:
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07/25/2003
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Publication #:
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Pub Dt:
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01/29/2004
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Title:
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METHOD FOR FABRICATING MOS TRANSISTORS
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Patent #:
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Issue Dt:
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02/14/2006
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Application #:
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10627300
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Filing Dt:
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07/25/2003
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Publication #:
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Pub Dt:
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08/12/2004
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Title:
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METHOD FOR FORMING SHORT-CHANNEL TRANSISTORS
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Patent #:
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Issue Dt:
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02/01/2005
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Application #:
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10746615
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Filing Dt:
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12/23/2003
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Title:
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CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME
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Patent #:
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Issue Dt:
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02/01/2005
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Application #:
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10746615
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Filing Dt:
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12/23/2003
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Title:
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CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME
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Patent #:
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Issue Dt:
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02/26/2008
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Application #:
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10969550
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Filing Dt:
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10/20/2004
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Publication #:
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Pub Dt:
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06/30/2005
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Title:
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METHOD FOR PREVENTING THE FORMATION OF A VOID IN A BOTTOM ANTI-REFLECTIVE COATING FILLING A VIA HOLE
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Assignee
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| 891-10 DAECHI-DONG |
| KANGNAM-KU |
| SEOUL, KOREA, REPUBLIC OF 135-523 |
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Correspondence name and address
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ANDREW D. FORTNEY, PH.D.
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LAW OFFICES OF ANDREW D. FORTNEY PH.D.PC
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7257 N. MAPLE AVENUE, SUITE 107
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FRESNO, CA 93720
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