Patent Assignment Details
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| Reel/Frame: | 036499/0769 | |
| Pages: | 9 |
| | Recorded: | 09/05/2015 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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07/10/2007
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Application #:
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10449669
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Filing Dt:
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05/30/2003
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Publication #:
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Pub Dt:
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12/02/2004
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Title:
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PARAMETER CHECKING METHOD FOR ON-CHIP ESD PROTECTION CIRCUIT PHYSICAL DESIGN LAYOUT VERIFICATION
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Assignee
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| 1128 FUSHAN AVE., |
| XIAOLAN ECONOMY AND TECHNOLOGY DEVELOPMENT DISTRICT |
| NANCHANG, CHINA |
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Correspondence name and address
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ALBERT WANG
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56 BOULDER CREEK WAY
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IRVINE, CA 92602
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